Patents by Inventor Yu-Kai Lin
Yu-Kai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11670546Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.Type: GrantFiled: March 4, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
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Publication number: 20230057550Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.Type: ApplicationFiled: August 19, 2022Publication date: February 23, 2023Inventors: Chih-Chuan CHEN, Wei-Hsiang TSAI, Chin-Yu CHEN, Ching-Cherng SUN, Jann-Long CHERN, Yu-Kai LIN
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Publication number: 20220285210Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
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Publication number: 20220208603Abstract: A method for forming a semiconductor device structure is provided. The method includes successively forming a first multi-layer etch stop structure and an insulating layer over a first conductive feature. The insulating layer and the first multi-layer etch stop structure are successively etched to form an opening substantially aligned to the first conductive feature. A second conductive feature is formed in the opening. The formation of the first multi-layer etch stop structure and the second multi-layer etch stop structure includes forming a first metal-containing dielectric layer, forming a silicon-containing dielectric layer over the first metal-containing dielectric layer, and forming a second metal-containing dielectric layer over the silicon-containing dielectric layer. The second metal-containing dielectric layer has a material that is different from the material of the first metal-containing dielectric layer.Type: ApplicationFiled: March 16, 2022Publication date: June 30, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG
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Patent number: 11282742Abstract: A semiconductor device structure is provided. The structure includes a conductive feature formed in an insulating layer. The structure also includes a first metal-containing dielectric layer formed over the insulating layer and covering the top surface of the conductive feature. The structure further includes a silicon-containing dielectric layer formed over the first metal-containing dielectric layer. In addition, the structure includes a second metal-containing dielectric layer formed over the silicon-containing dielectric layer. The second metal-containing dielectric layer includes a material that is different than the material of the first metal-containing dielectric layer.Type: GrantFiled: October 17, 2019Date of Patent: March 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
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Publication number: 20220058359Abstract: A fingerprint sensing module has a fingerprint sensor and a cover. The main color layer and the pattern layer are arranged between the cover and the fingerprint sensor. The pattern layer constitutes a predetermined pattern that is used to present the pattern of the button. The both sides of the main color layer are flush with both sides of the pattern layer, so that the capacitance variations in the corresponding pattern layer and the main color layer pass through the medium with the same thickness, and have an approximate capacitance variation mode. Thus, the sensed fingerprint image truly reflect the detected fingerprint image without being affected by the preset pattern, and a pattern layer with a certain thickness is used to enhance the color saturation presented by the predetermined pattern.Type: ApplicationFiled: July 9, 2021Publication date: February 24, 2022Applicant: ELAN MICROELECTRONICS CORPORATIONInventor: Yu-Kai LIN
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Publication number: 20210288002Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chia-Hao SUNG, Hsuan-Yu CHEN, Yu-Kai LIN
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Publication number: 20210280460Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.Type: ApplicationFiled: May 10, 2021Publication date: September 9, 2021Inventors: Szu-Ping Tung, Yu-Kai Lin, Jen Hung Wang, Shing-Chyang Pan
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Patent number: 11024586Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.Type: GrantFiled: January 22, 2019Date of Patent: June 1, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chia-Hao Sung, Hsuan-Yu Chen, Yu-Kai Lin
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Patent number: 11004734Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.Type: GrantFiled: November 4, 2019Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Ping Tung, Yu-Kai Lin, Jen Hung Wang, Shing-Chyang Pan
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Publication number: 20210118728Abstract: A semiconductor device structure is provided. The structure includes a conductive feature formed in an insulating layer. The structure also includes a first metal-containing dielectric layer formed over the insulating layer and covering the top surface of the conductive feature. The structure further includes a silicon-containing dielectric layer formed over the first metal-containing dielectric layer. In addition, the structure includes a second metal-containing dielectric layer formed over the silicon-containing dielectric layer. The second metal-containing dielectric layer includes a material that is different than the material of the first metal-containing dielectric layer.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG
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Patent number: 10879215Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.Type: GrantFiled: March 8, 2019Date of Patent: December 29, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
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Publication number: 20200235056Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.Type: ApplicationFiled: January 22, 2019Publication date: July 23, 2020Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chia-Hao SUNG, Hsuan-Yu CHEN, Yu-Kai LIN
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Patent number: 10656321Abstract: A light guiding structure of a backlight device having an insulation substrate, a micro LED, a reflecting layer, a light guiding layer and reflecting film. An illuminating surface is formed on the insulation substrate. The reflecting layer is stacked on the insulation substrate and stacked with the light guiding layer. The micro LED is arranged on the illuminating surface and illuminating toward a direction perpendicular to the illuminating surface. The reflecting film is stacked on the illuminating surface and covering on the micro LED, an edge of the light guiding layer is stacked between an edge of the reflecting film and the reflecting layer, a reflecting slope is defined on the reflecting film and extended from the micro LED to the edge of the light guiding layer. Light projected from the micro LED is reflected into the light guiding layer by the reflecting slope of the reflecting film.Type: GrantFiled: June 22, 2019Date of Patent: May 19, 2020Assignee: SUZHOU LUUMII LTD.Inventors: Yu-Kai Lin, Chen-Fang Kang
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Patent number: 10596963Abstract: A fatigue alarm apparatus having a fatigue detector, a control unit and a stimulus alarm generator is illustrated. The fatigue detector detects whether a driver is drowsy. The control unit is electrically connected to the fatigue detector and the stimulus alarm generator. When the fatigue detector detects that the driver is drowsy, the stimulus alarm generator controlled by the control unit to generate two stimulus alarms having a rest time period therebetween, and then, after an interval period elapses, the control unit determines whether an alarming procedure of generating the two stimulus alarms is to be interrupted or repeated, wherein the rest time period is less than the interval period.Type: GrantFiled: October 25, 2018Date of Patent: March 24, 2020Assignee: LATTICE ENERGY TECHNOLOGY CORPORATIONInventors: Ta-Yi Chien, Pai-Hsiang Cheng, Ying-Ju Lai, Chang-Sheng Lin, Yung-Chou Chen, Guan-Hua Chen, Hsiang-Fu Fan, Yu-Kai Lin, Wen-Jing Xie
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Publication number: 20200066581Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.Type: ApplicationFiled: November 4, 2019Publication date: February 27, 2020Inventors: Szu-Ping Tung, Yu-Kai Lin, Jen Hung Wang, Shing-Chyang Pan
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Patent number: 10468297Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.Type: GrantFiled: April 27, 2018Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Ping Tung, Yu-Kai Lin, Jen Hung Wang, Shing-Chyang Pan
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Publication number: 20190333807Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Inventors: Szu-Ping Tung, Yu-Kai Lin, Jen Hung Wang, Shing-Chyang Pan
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Patent number: 10389249Abstract: A switching regulator having adjustable inductor current threshold employs a control method which includes: (S1) determining whether an output voltage is greater than a reference voltage or determining whether a switching frequency of the power stage is smaller than a predetermined lower frequency limit, and (S2) when it is determined yes in the step (S1), adjusting the inductor current threshold, such that the switching regulator operates under a pseudo discontinuous conduction mode (PDCM) wherein the switching frequency is not smaller than the predetermined lower frequency limit. Consequently, when the switching regulator operates under a light load mode, an optimum balance between a total power consumption and switching noise interference will be ensured.Type: GrantFiled: June 15, 2018Date of Patent: August 20, 2019Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Hong-Wei Huang, Yu-Kai Lin, Wei-Chuan Wu
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Publication number: 20190228930Abstract: A luminous press key module includes a bottom plate, a keycap, a membrane circuit board, and one or more micro LEDs. The keycap is installed above the bottom plate, the membrane circuit board is installed between the bottom plate and the keycap, and the micro LED is installed and electrically coupled to the membrane circuit board and arranged corresponding to the keycap. The micro LED can be installed on the membrane circuit board directly to omit the component of the conventional light guide plate, so as to realize a light, thin, short and compact design of the luminous press key module.Type: ApplicationFiled: August 4, 2018Publication date: July 25, 2019Inventor: Yu-Kai LIN