Abstract: A mixture of octanols, nonanols and decanols is useful for the preparation of alkoxylates, which alkoxylates may be used as surfactants, which surfactants have surprisingly good biodegradability.

Abstract: A system, method, and computer readable medium with instructions for verifying an original layout are disclosed. The original layout includes cells arranged in a cell hierarchy, front-end-of-line (FEOL) layers, and back-end-of-line (BEOL) layers. In one embodiment, a reduced layout is generated by trimming out cells below a top tier of the cell hierarchy and filtering out the FEOL layers. A text-based short check is executed on the reduced layout. Next, an augmented reduced layout is generated. The augmented reduced layout includes pin information for cells in a second tier connected to the top tier. An interconnectivity check is then executed on the augmented reduced layout based on a schematic for the circuit. Afterwards, a result (e.g., location of short or connectivity mismatch) based on at least one of the text-based short check and the interconnectivity check is outputted. A conventional LVS check may then be executed.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation layer covering the magnetic element and a portion of the semiconductor substrate. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding edges of the magnetic element.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate includes a first region and a second region. The semiconductor device structure includes a first conductive structure formed over the first region of the substrate and a bottom magnetic layer formed over the second region of the substrate. The semiconductor device structure also includes a second conductive structure formed over the bottom magnetic layer and a first insulating layer formed over a sidewall surface of the first conductive structure. The semiconductor device structure further includes a second insulating layer formed over the first insulating layer, and the second insulating layer has a stair-shaped structure.

Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

Abstract: A method for suppressing the formation of ammonia comprising providing a carrier material to a container having a headspace; providing a bacteria and an odor inhibitor to the carrier material, the bacteria comprising Staphylococcus-xylosus and/or Staphylococcus-cohnii bacteria, and the odor inhibitor comprising an aminopolycarboxylic acid compound and a polyprotic acid compound, wherein at least one of the aminopolycarboxylic acid compound or the polyprotic acid compound is the salt form of the acid; and applying animal waste to the carrier material; wherein there is a 5 to 98 percent improvement of ammonia content in the headspace as compared to an untreated control comprising a container containing the carrier material and the bacteria and not contain the odor inhibitor. An ammonia suppressing composition.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a passivation layer over a semiconductor substrate. The method also includes forming a magnetic element over the passivation layer. The method further includes forming an isolation layer over the magnetic element and the passivation layer. The isolation layer includes a polymer material. In addition, the method includes forming a conductive line over the isolation layer, and the conductive line extends across the magnetic element.

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Abstract: A mixture of octanols, nonanols and decanols is useful for the preparation of alkoxylates, which alkoxylates may be used as surfactants, which surfactants have surprisingly good biodegradability.

Abstract: A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic. The detected mismatch is a device or net represented by a first node in the first graph and a corresponding second node in the second graph. The LVS tool assigns a first value to the first node and to the second node. The LVS tool iterates through nodes in the first graph and nodes in the second graph to assign values based on the first value, according to a graph coloring algorithm, until reaching a third node of the first graph and a corresponding fourth node of the second graph that are assigned different values. The LVS tool generates an output identifying the third node and the fourth node as a root cause of the detected mismatch.

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.

Abstract: A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.

Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.

Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a first side and a second side opposite to the first side; forming a recess extending between the first side and the second side; and disposing a conductive material in the recess to form a conductive via, wherein the conductive via includes an interface, a first portion adjacent to the first side and a second portion adjacent to the second side, the interface is disposed between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.

Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.

Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.