Abstract: A triboelectric generator can include respective contact members including a first contact member and second contact member. The respective contact members can be movable with respect to each other such that the respective contact members separate from each other in a first configuration and contact each other in a second configuration. The first contact member can include a first conductive layer and a contact layer. The second contact member can be spaced apart from the first contact member in the first configuration and can include an insulating contact layer and a second conductive layer. The insulating contact layer can be configured to come into contact with the contact layer of the first contact member and the transition of the respective contact members from the first configuration to the second configuration can create triboelectric charges. In some examples, the first contact member can include a non-contact insulating layer.

Abstract: Disclosed are a method and a device for low latency communication in a communication system. An operation method of a base station comprises the steps of: transmitting first scheduling information of data units, transmitted through A sections in subframe #n, to a terminal through a first control channel in subframe #n; transmitting the data units to the terminal through the A sections; and transmitting second scheduling information of data unit(s), transmitted through B section(s) in subframe #(n+k) following subframe #n, to the terminal through a second control channel in subframe #(n+k). Therefore, the performance of the communication system can be improved.

Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.

Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.

Abstract: An optical radar includes an optical-signal receiving unit and an optical-signal pickup unit. The optical-signal receiving unit is configured to receive a reflected light. The optical-signal pickup unit is coupled to the optical-signal receiving unit and includes a first optical-signal filtering circuit and a second optical-signal filtering unit. The first optical-signal filtering circuit is configured to filter out a first interference pulse of the reflected light, wherein the first interference pulse has a first interference voltage value higher than a reference voltage. The second optical-signal filtering circuit is coupled to the first optical-signal filtering circuit and configured to generate a clock signal comprising a clock pulse; and filter out a second interference pulse that does not match the clock pulse in time point from the reflected light.

Abstract: An in-memory-computing method for a memory device includes: storing weight values in cascaded computing cells each including first and second computing memory cells, wherein the first computing memory cells are cascaded in series into a first computing memory cell string and the second computing memory cells are cascaded in series into a second computing memory cell string: receiving input values by the first and the second computing memory cell strings; performing a first logic operation on the input values and the weight values by the first computing memory cell string to generate a first logic operation result, and performing a second logic operation on the input values and the weight values by the second computing memory cell string to generate a second logic operation result: and performing a third logic operation on the first and the second logic operation results to generate an output logic operation result.

Abstract: A method, comprising: detecting an outage of at least one functionality in a live streaming; performing an first operation toward a second user terminal; storing data of the first operation in a database of the first user terminal; and displaying an effect corresponding to the first operation during the outage. The present disclosure may store the data of operation performed by the user terminal during outage and process the operation after the outage is recovered. Therefore, the streamers and viewers may feel interested and satisfied, instead of feeling anxious, and the user experience may be enhanced.

Abstract: Disclosed are techniques for wireless sensing. In an aspect, a method for reconfigurable intelligent surface (RIS)-assisted sensing performed by a base station (BS) includes configuring one or more reciprocal RIS beam pairs for sensing, wherein each of the one or more reciprocal RIS beam pairs comprises a downlink (DL) beam having a DL angle of departure (DL AoD) from a RIS controlled by a first set of control voltages and an uplink (UL) beam having an UL AoD from the RIS controlled by a second set of control voltages. The BS may send, to the RIS, information identifying the one or more reciprocal RIS beam pairs. The BS may perform monostatic sensing using at least one of the one or more reciprocal RIS beam pairs.

Abstract: A pixel connected to a first scan line includes a light-emitting element including an anode and a cathode, a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node, a first capacitor connected between the first node and a second node, a second transistor connected between the second electrode of the first transistor and the first node including a gate electrode connected to the first scan line, a third transistor including a first electrode, a second electrode connected to the second node, and a gate electrode connected to the first scan line, and a fourth transistor including a first electrode connected to a first driving voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the first scan line.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: A plasma processing apparatus for semiconductor processing includes an injector holder configured to removably mate with a structure defining an interior chamber of a plasma processing apparatus. The injector holder defines a first opening. A sleeve is configured to be received within the first opening, and the sleeve defines a second opening. A gas injector is configured to be received within the second opening of the sleeve.

Abstract: A laser machining device includes a pulsed laser generator, an accommodation chamber, a bandwidth broadening unit and a pulse compression unit. The pulsed laser generator is configured to emit a pulsed laser. The accommodation chamber has a gas inlet. The bandwidth broadening unit is disposed in the accommodation chamber, and is configured to broaden a frequency bandwidth of the pulsed laser to obtain a broad bandwidth pulsed laser. The pulse compression unit is disposed in the accommodation chamber. The bandwidth broadening unit and the pulse compression unit are arranged in order along a laser propagation path, and the pulse compression unit is configured to compress a pulse duration of the broad bandwidth pulsed laser.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode layer on the p-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode. Preferably, the gate electrode includes an inclined sidewall.

Abstract: Provided are a novel boron-containing compound and an electrolyte solution additive for a secondary battery including the same. The electrolyte solution for a secondary battery provided in one embodiment includes the novel boron-containing compound, thereby suppressing the decomposition of an electrolyte solution to improve the capacity and the life characteristics of a battery.

Abstract: A system includes one or more data processors configured to run a basic input/output system (BIOS) service and a bootloader configuration manager for tuning kernel parameters. The system further includes a non-transitory computer-readable storage medium containing instructions which, when executed on the one or more data processors, cause the one or more data processors to perform operations. The operations include receiving administrative inputs and checking the administrative inputs against a checklist to determine whether any errors are introduced by the administrative inputs. The operations further include writing the administrative inputs to a temporal configuration file in response to no errors being introduced by the administrative inputs. The operations further include exporting the temporal configuration file to a designated output path. The exported temporal configuration file includes kernel parameter settings for configuring a bootloader of a computing device.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.

Abstract: An antenna apparatus includes a feeding antenna inside an electronic device and one or more antenna elements, such as a floating metal antenna, disposed on a rear cover of the electronic device. The floating metal antenna and a feeding antenna inside the electronic device may form a coupling antenna structure. The feeding antenna may be an antenna fastened on an antenna support (which may be referred to as a support antenna). The feeding antenna may alternatively be a slot antenna formed by slitting on a metal middle frame of the electronic device. The antenna apparatus may be implemented in limited design space, thereby effectively saving antenna design space inside the electronic device. The antenna apparatus may generate excitation of a plurality of resonance modes, so that antenna bandwidth and radiation characteristics can be improved.