Patents by Inventor Yu Lee

Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299052
    Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Inventors: Chih-Lin CHEN, Hui-Yu LEE, Fong-Yuan CHANG, Po-Hsiang HUANG, Chin-Chou LIU
  • Patent number: 11765852
    Abstract: A mounting base is provided. The mounting base is adapted to be selectively affixed to different supporting structures. The mounting base includes a mounting base body, a first hook, a second hook and a rotatable member. The first hook is formed on the mounting base body. The second hook is formed on the mounting base body. The rotatable member is pivoted on the mounting base body. The rotatable member is adapted to be rotated between a first orientation and the second orientation relative to the mounting base body. When the rotatable member is in the first orientation, the rotatable member is restricted by the mounting base body. When the rotatable member is in the second orientation, the rotatable member is restricted by the mounting base body.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: September 19, 2023
    Assignee: WISTRON NEWEB CORP.
    Inventors: Chun-Yu Lee, Sheng-Yuan Chen
  • Patent number: 11755439
    Abstract: A memory controller coupled to a memory device and configured to control access operations of the memory device includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and configured to set a value of a predetermined parameter to a specific value after the memory controller powers up and start to perform a link flow to try to establish a transmission link via the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface and the predetermined parameter is related to reception of the host interface. After the link flow is completed, the microprocessor is further configured to identify an object device with which the host interface establishes the transmission link according to the specific value and at least one of a plurality of attribute parameters associated with the transmission link.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: September 12, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Cheng-Yu Lee, Te-Kai Wang
  • Patent number: 11752799
    Abstract: The present disclosure relates to the technical field of decorations, in particular to an ornament. The ornament includes a plurality of main bodies. Each main body includes a frame with a regular pentagonal cross section and a regular pentagonal sheet arranged at the bottom of the frame; five sides of the frame are symmetrically provided with connection elements respectively; and the plurality of main bodies are spliced by the adjacent connection elements to form a spherical object. The purpose of the present disclosure is to provide an ornament, which solves the problem that the traditional hollow spherical decorations are easy to collapse during placement.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: September 12, 2023
    Inventor: Che-Yu Lee
  • Patent number: 11754794
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a waveguide on a first side of the substrate. The semiconductor device further includes a photodetector (PD) on a second side of the substrate, opposite the first side of the substrate. The semiconductor device further includes an optical through via (OTV) optically connecting the PD with the waveguide, wherein the OTV extends through the substrate from the first side of the substrate to the second side of the substrate.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hao Chen, Chung-Ming Weng, Tsung-Yuan Yu, Hui Yu Lee, Hung-Yi Kuo, Jui-Feng Kuan, Chien-Te Wu
  • Publication number: 20230282521
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate and a first epitaxial structure over the first fin structure. The semiconductor device structure also includes a second epitaxial structure over the second fin structure. The semiconductor device structure further includes a dielectric fin over the semiconductor substrate. The dielectric fin is between the first fin structure and the second fin structure. The dielectric fin has an inner portion and a protective layer. The protective layer extends along sidewalls and a bottom of the inner portion, and the protective layer has a dielectric constant higher than that of the inner portion.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 7, 2023
    Inventors: Kun-Yu LEE, Chunyao WANG, Chi On CHUI
  • Publication number: 20230282390
    Abstract: A flexible flat cable includes a low-dielectric adhesive layer, a plurality of conductors, two shielding layers and two insulating protective layers. These conductors are located inside the low-dielectric adhesive layer and are spaced apart. The two shielding layers are laminated individually to the upper and lower surfaces of the low-dielectric adhesive layer. The two insulating protective layers are laminated individually to the two shielding layers.
    Type: Application
    Filed: April 29, 2022
    Publication date: September 7, 2023
    Inventors: HSING-YU LEE, KUAN-WU CHEN
  • Patent number: 11749584
    Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsiang Huang, Chin-Chou Liu, Chin-Her Chien, Fong-yuan Chang, Hui Yu Lee
  • Patent number: 11750261
    Abstract: An analog beamformer used for array antenna and an operating method thereof are provided. The analog beamformer used for array antenna includes an intermediate-frequency amplifying circuit, multiple local oscillators, multiple mixers, multiple radio-frequency amplifying circuits, and a frequency locking circuit. The analog beamformer uses a master-oscillator and multiple slave-oscillators which embed a resonant network of frequency-and-phase-locking. The intermediate-frequency amplifying circuit receives a baseband signal to provide an intermediate-frequency signal. Power supplies or grounding ports of different local oscillators are connected together to provide multiple local-oscillating signals with consistent frequency but different phases. The mixers individually receive the intermediate-frequency signal and one of the local-oscillating signals to provide multiple mixed signals.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: September 5, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Janne-Wha Wu, Tang-Yu Lee, Ming Jie Yu
  • Patent number: 11748629
    Abstract: A computing device for handling anomaly detection, comprises an encoder, for receiving an input image, to generate a first latent vector comprising a semantic latent vector and a visual appearance latent vector according to the input image and at least one first parameter of the encoder; and a training module, coupled to the encoder, for receiving the input image and the first latent vector, to update the at least one first parameter according to the input image and the first latent vector and a loss function.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: September 5, 2023
    Assignee: Moxa Inc.
    Inventors: Wei-Yu Lee, Yu-Chiang Wang
  • Publication number: 20230274143
    Abstract: A method for rehearsal-free continual learning includes obtaining a set of training samples where training sample in the set of training samples is associated with a respective task of a plurality of different tasks. The method includes obtaining a task-invariant prompt representative of learned knowledge common to each respective task of the plurality of different tasks. The method includes, for each respective task of the plurality of different tasks, obtaining a respective task-specific prompt representative of learned knowledge specific to the respective task. The method includes, during each of one or more training iterations, for each respective training sample in the set of training samples, selecting the respective task-specific prompt representative of the respective task of the respective training sample and training a model using the task-invariant prompt and the selected respective task-specific prompt.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 31, 2023
    Applicant: Google LLC
    Inventors: Zizhao Zhang, Zifeng Wang, Chen-Yu Lee, Ruoxi Sun, Sayna Ebrahimi, Xiaoqi Ren, Guolong Su, Vincent Perot, Tomas Pfister, Han Zhang
  • Publication number: 20230273500
    Abstract: An optical structure is provided. The optical structure includes a first substrate, a second substrate, a sealant, a light-modulating layer and a first conductive layer. The second substrate is disposed opposite to the first substrate. The sealant is disposed between the first substrate and the second substrate. The sealant is disposed around to form a visible area. The light-modulating layer is disposed in the visible region between the first substrate and the second substrate. The first conductive layer has a plurality of strip structures. The plurality of strip structures are disposed in the visible area to form an effective area. The visible area partially overlaps the effective area.
    Type: Application
    Filed: January 12, 2023
    Publication date: August 31, 2023
    Inventors: Te-Yu LEE, Yu-Tsung LIU, Cheng-Hsueh HSIEH, Wei-Ju LIAO
  • Publication number: 20230273491
    Abstract: The electronic device includes a substrate; an active layer disposed above the first substrate; a first signal line disposed above the substrate; and a conductive pattern. The conductive pattern is in electrical contact with the active layer, wherein the conductive pattern includes a first side extending in a first direction, a second side extending in the first direction, and a third side connected between the first side and the second side, and wherein the third side includes a part that the part is not parallel to the first direction and not perpendicular to the first direction, and the part is located out of the first signal line.
    Type: Application
    Filed: May 10, 2023
    Publication date: August 31, 2023
    Inventors: Chung-Wen YEN, Yu-Tsung LIU, Chao-Hsiang WANG, Te-Yu LEE
  • Publication number: 20230275040
    Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
  • Patent number: 11740564
    Abstract: A method comprises loading a wafer onto a wafer chuck of a lithography apparatus, projecting an extreme ultraviolet light through an opening of a frame structure of the lithography apparatus, onto the wafer, and introducing an airflow from an air curtain module on the wafer chuck toward the frame structure, wherein the air curtain module surrounds the wafer. The airflow forms an air curtain around the wafer, and shields the wafer from contaminants from the frame structure or a wafer stage.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tao-Hsin Chen, Chia-Yu Lee
  • Patent number: 11740415
    Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Chen, Hui-Yu Lee, Chung-Ming Weng, Jui-Feng Kuan, Chien-Te Wu
  • Patent number: 11740504
    Abstract: A curved panel includes a first curved substrate, a second curved substrate, a curved coverlens, and an adhesive structure. The first curved substrate and the second curved substrate are overlapped with each other. First to fourth sidewalls of the first curved substrate correspond to fifth to eighth sidewalls of the second curved substrate, respectively. The first to third sidewalls of the first curved substrate extend beyond the fifth to seventh sidewalls of the second curved substrate, respectively. The second curved substrate is located between the curved coverlens and the first curved substrate. The second curved substrate is bonded to the curved coverlens through an adhesive layer. The adhesive structure is located between the first curved substrate and the curved coverlens and is laterally located between the first sidewall and the fifth sidewall, between the second sidewall and the sixth sidewall, and between the third sidewall and the seventh sidewall.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: August 29, 2023
    Assignee: AUO Corporation
    Inventors: Chun-Yu Lee, Sheng-Yuan Chiu, Yen-Chang Chen, Po-Shu Huang, Ho-Hsiang Wang
  • Publication number: 20230268301
    Abstract: A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Hui-Yu Lee
  • Publication number: 20230268353
    Abstract: An electronic device is provided. The electronic device includes a substrate, a first conductive layer disposed on the substrate, a planarization layer disposed on the first conductive layer, an electric element, and a second conductive layer disposed on the planarization layer. The first conductive layer and the second conductive layer include an output line and a control line, respectively. The electric element is used to produce a first signal. The electronic device further includes a switching element, which is used to receive the first signal and output the first signal to the output line according to a second signal of the control line. The output line and the control line partially overlap.
    Type: Application
    Filed: January 12, 2023
    Publication date: August 24, 2023
    Inventors: Ya-Li TSAI, Hui-Ching YANG, Yang-Jui HUANG, Yu-Tsung LIU, Te-Yu LEE
  • Publication number: 20230265635
    Abstract: A multi-piece pre-assembled raft foundation is provided and includes pre-assemble bottom layer rebars of foundation slab, foundation steel columns, upper layer rebars of the foundation slab, and foundation rebars. The pre-assembled raft foundation is transported to a construction site for final assembly. A construction method of the multi-piece pre-assembled raft foundation is also provided.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 24, 2023
    Inventors: Fu-Yuan Lu, Ju-Chuan Ko, Ying-Ying Lu, Chien-Hui Lu, Cheng-Yu Lee, Mei-Hua Chien, Guang-Le Su, Sen Taner