Patents by Inventor Yu Lei

Yu Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10691849
    Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
  • Publication number: 20200178511
    Abstract: The present invention relates to a pest monitoring method based on machine vision. The method includes the following steps: arranging a pest trap at a place where pests gather, and setting an image acquisition device in front of the pest trap to acquire an image; identifying a pest in the acquired image, and obtaining a number of pests; extracting multiple suspicious pest images from a region of each identified pest in the image, and determining identification accuracy of each suspicious pest image, if the number of pests is greater than or equal to a preset threshold for the number of pests; and calculating a predicted level of pest damage based on the number of pests and the identification accuracy of each suspicious pest image. The present invention acquires a pest image automatically through the image acquisition device in front of the pest trap.
    Type: Application
    Filed: December 25, 2017
    Publication date: June 11, 2020
    Inventors: Yu TANG, Shaoming LUO, Zhenyu ZHONG, Huan LEI, Chaojun HOU, Jiajun ZHUANG, Weifeng HUANG, Zaili CHEN, Jintian LIN, Lixue ZHU
  • Patent number: 10679697
    Abstract: A read circuit of storage class memory comprises: an array; a read reference circuit, having the same bit line parasitic parameters as the array, having the same read transmission gate parasitic parameters as the array, used to generate a read reference current; a sense amplifier, providing the same current mirror parasitic parameters as the reference side, used to generate a read current from a selected memory cell, compare the said read current with the said read reference current and output a readout result. In the present invention, the said read current and the said read reference current are generated at the same time, the transient curve of the said read reference current is between the low resistance state read current and the high resistance state read current from an early stage. The present invention largely reduces the read access time, has a good process variation tolerance, has a wide application, and is easy to be used in the practical product.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: June 9, 2020
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCE
    Inventors: Yu Lei, Houpeng Chen, Xi Li, Qian Wang, Zhitang Song
  • Patent number: 10673194
    Abstract: A manufacturing method of connector structure including the following steps is provided. First, providing a dielectric layer having. Then, forming a first adhesive layer and a second adhesive layer on two opposite sides of the dielectric layer respectively. Then, providing at least one first conductive elastic cantilever and at least one second conductive elastic cantilever, wherein the first conductive elastic cantilever comprises a first fixing end portion and a first free end portion, and the second conductive elastic cantilever comprises a second fixing end portion and a second free end portion. Then, fixing the first fixing end portion and the second fixing end portion to the first adhesive layer and the second adhesive layer respectively, wherein the first fixing end portion is aligned with the second fixing end portion. Afterward, forming at least one conductive via for electrically connecting the first conductive elastic cantilever with the second conductive elastic cantilever.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 2, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hsiang Chuang, Guodong Li, He Lei, Jianyu Zhang
  • Publication number: 20200168568
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.
    Type: Application
    Filed: June 14, 2019
    Publication date: May 28, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
  • Patent number: 10665450
    Abstract: Methods and apparatus for forming a semiconductor structure, including depositing a doping stack having a first surface atop a high-k dielectric layer, wherein the doping stack includes at least one first metal layer having a first surface, at least one second metal layer comprising a first aluminum dopant and a first surface, wherein the second metal layer is atop the first surface of the first metal layer, and at least one third metal layer atop the first surface of the second metal layer; depositing an anneal layer atop the first surface of the doping stack; annealing the structure to diffuse at least the first aluminum dopant into the high-k dielectric layer; removing the anneal layer; and depositing at least one work function layer atop the first surface of the doping stack.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: May 26, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yixiong Yang, Paul F. Ma, Wei V. Tang, Wenyu Zhang, Shih Chung Chen, Chen Han Lin, Chi-Chou Lin, Yi Xu, Yu Lei, Naomi Yoshida, Lin Dong, Siddarth Krishnan
  • Publication number: 20200158522
    Abstract: A method for determining a new route in a map may include obtaining a plurality of original motion sequences. Each of the plurality of original motion sequences may include a departure location and a destination. The method may also include obtaining current route map information corresponding to the plurality of original motion sequences. The method may also include determining, from the plurality of original motion sequences, one or more candidate motion sequences, which have a same departure location and a same destination but being different from the current route map information. The method may also include determining a new route between the same departure location and the same destination based on the one or more candidate motion sequences.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Applicant: BEIJING DIDI INFINITY TECHNOLOGY AND DEVELOPMENT CO., LTD.
    Inventors: Yu WANG, Zhou YE, Duokun ZHANG, Min LI, Hui LEI, Rui GUO
  • Patent number: 10658482
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Publication number: 20200152599
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG
  • Publication number: 20200152183
    Abstract: The present disclosure is related to systems and methods for processing a conversation message. The method includes receiving the conversation message from the client terminal via the data exchange port. The method also includes determining whether the conversation message is associated with at least one pre-set topic category. The method also includes determining a topic category associated with the conversation message based on a prior conversation message in response to a determination that the conversation message is not associated with at least one pre-set topic category. The method further includes determining a semantics associated with the conversation message based on the topic category and the conversation message. The method still further includes generating a response to the conversation message based on the determined semantics to be transmitted to the service system implemented on the client terminal via the data exchange port.
    Type: Application
    Filed: January 19, 2020
    Publication date: May 14, 2020
    Applicant: BEIJING DIDI INFINITY TECHNOLOGY AND DEVELOPMENT CO., LTD.
    Inventors: Yu WANG, Zhou YE, Duokun ZHANG, Min LI, Hui LEI, Rui GUO
  • Publication number: 20200142880
    Abstract: Embodiments of the present disclosure provide a method, a device and a computer program product for data processing. The method comprises in response to data associated with an object being stored in the storage location, generating an entry indicating a first association relationship between the data and a storage location. The method further comprises generating metadata of the object, the metadata indicating a second association relationship between the object and the entry. Further, the method comprises in response to the first association relationship between the data and the storage location being changed, updating the entry independent of the metadata. Embodiments of the present disclosure may avoid the huge cost caused by changing metadata multiple times and reduce the system load and the impacts to the front end load.
    Type: Application
    Filed: June 14, 2019
    Publication date: May 7, 2020
    Inventors: Ao Sun, Lu Lei, Wesley Wei Sun, Gary Jialei Wu, Yu Teng
  • Publication number: 20200144056
    Abstract: Methods and apparatus for forming a cobalt layer on a substrate disposed in a process chamber are disclosed herein. In the present disclosure, exposing a substrate to a first process gas including a bonding agent in an amount sufficient to facilitate bonding or adhesion of cobalt to a first surface of the substrate; and depositing cobalt upon the first surface of the substrate to form a cobalt layer is disclosed. The use of one or more silanes or molybdenum carbonyl compositions facilitate bonding or adhesion of cobalt to a first surface of the substrate. In the present disclosure, suitable substrates include substrates that do not easily bond or adhere to cobalt, such as titanium nitrate or tantalum nitrate.
    Type: Application
    Filed: November 3, 2018
    Publication date: May 7, 2020
    Inventors: WEI LEI, TAE HONG HA, BYUNGHOON YOON, YU LEI
  • Publication number: 20200133654
    Abstract: A method for remotely updating firmware of a field programmable gate array (FPGA) includes: by a controller, transmitting a storing instruction and relaying an entry of configuration data received from a remote device to a processor of the FPGA; by the processor, performing an updating subtask to store a file segment recorded in the entry of configuration data in an update-storage area indicated by location information recorded in the entry of configuration data; by the controller, determining whether the processor has successfully completed the updating subtask, and when affirmative, enabling the remote device to transmit another entry of configuration data; and repeating the aforementioned steps.
    Type: Application
    Filed: September 4, 2019
    Publication date: April 30, 2020
    Applicant: Mitac Computing Technology Corporation
    Inventors: Yun-Shan LEI, Lung-Chiao CHANG, Cheng-Yu CHUANG, Peng XIE
  • Publication number: 20200129640
    Abstract: The present invention provides methods, compositions, systems, and kits comprising nano-satellite complexes and/or serum albumin carrier complexes, which are used for modulating antigen-specific immune response (e.g., enhancing anti-tumor immunity). In certain embodiments, the nano-satellite complexes comprise: a) a core nanoparticle complex comprising a biocompatible coating surrounding a nanoparticle core; b) at least one satellite particle attached to, or absorbed to, the biocompatible coating; and c) an antigenic component conjugated to, or absorbed to, the at least one satellite particle component. In certain embodiments, the complexes further comprise: d) an type I interferon agonist agent. In some embodiments, the serum albumin complexes comprise: a) at least part of a serum albumin protein, b) an antigenic component conjugated to the carrier protein, and c) a type I interferon agonist agent.
    Type: Application
    Filed: June 1, 2018
    Publication date: April 30, 2020
    Inventors: Yu Lei, Yee Sun Tan, Kanokwan Sansanaphongpricha, Duxin Sun, Hongwei Chen, Hongxiang Hu
  • Publication number: 20200127146
    Abstract: Various embodiments of the present disclosure are directed towards a varactor comprising a reduced surface field (RESURF) region. In some embodiments, the varactor includes a drift region, a gate structure, a pair of contact regions, and a RESURF region. The drift region is within a substrate and has a first doping type. The gate structure overlies the drift region. The contact regions are within the substrate and overlie the drift region. Further, the contact regions have the first doping type. The gate structure is laterally sandwiched between the contact regions. The RESURF region is in the substrate, below the drift region, and has a second doping type. The second doping type is opposite the first doping type. The RESURF region aids in depleting the drift region under the gate structure, which decreases the minimum capacitance of the varactor and increases the tuning range of the varactor.
    Type: Application
    Filed: June 7, 2019
    Publication date: April 23, 2020
    Inventors: Liang-Yu Su, Chih-Wen Yao, Hsiao-Chin Tuan, Ming-Ta Lei
  • Publication number: 20200126615
    Abstract: A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.
    Type: Application
    Filed: April 25, 2017
    Publication date: April 23, 2020
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: YU LEI, HOUPENG CHEN, ZHITANG SONG
  • Publication number: 20200118256
    Abstract: A display method and a display device are provided. The display method may be applied to a display device having a lens unit and a display unit for normal display, and may include steps of: detecting a first distance between the lens unit and the display unit; calculating correction information according to the first distance and transmitting the correction information to the display unit; and displaying a corrected image by the display unit according to the correction information, so that the corrected image is converged into eyes of a user via the lens unit, wherein the corrected image is obtained by correcting an original image according to the first distance.
    Type: Application
    Filed: January 2, 2019
    Publication date: April 16, 2020
    Inventors: Yukun SUN, Xuefeng WANG, Jinghua MIAO, Wenyu LI, Jinbao PENG, Bin ZHAO, Lixin WANG, Xi LI, Qingwen FAN, Jianwen SUO, Yali LIU, Yu LEI, Yakun WANG, Hao ZHANG, Lili CHEN
  • Publication number: 20200104054
    Abstract: Embodiments of the present disclosure provide methods, apparatuses, a system and computer program products for managing storage units. According to embodiments of the present disclosure, it is determined whether a first storage unit allocated at a first node is reclaimable, wherein data in the first storage unit is backed up to a second storage unit at a second node. In response to determining that the first storage unit is reclaimable, a condition to be satisfied for reclaiming the second storage unit is determined. A command indicating the condition is sent to the second node, such that the second node reclaims the second storage unit in response to the condition being satisfied. Moreover, in response to the command being sent, the first storage unit is reclaimed. The embodiments of the present disclosure enable timely reclaiming of storage units, thereby improving utilization of the storage space effectively.
    Type: Application
    Filed: March 19, 2019
    Publication date: April 2, 2020
    Inventors: Lu Lei, Ao Sun, Wesley Wei Sun, Gary Jialei Wu, Yu Teng, Chun Xi Kenny Chen
  • Patent number: 10568304
    Abstract: A steel structure cage for marine crustacean aquaculture and integration thereof into a vertical fish-crustacean aquaculture system are disclosed. The steel structure cage includes a steel frame, top, side and bottom net systems, a ballast tank system, and steel grooves. The steel frame includes internal and external steel frames. The steel grooves are fixed on upper and lower ends of the internal steel frame. Edges of the top and bottom net systems are respectively fixed into the corresponding steel grooves. The side net is welded on the internal steel frame. The ballast tank system is arranged between the internal and external steel frames. A HDPE cage is moored to the steel structure cage to form a vertical aquaculture system. Whereby, an ideal culturing environment for marine crustaceans is given and the objective of vertical aquaculture “culturing fish at top water layers and culturing prawns (crabs or cowries) at bottom water layers” can be fulfilled.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 25, 2020
    Assignee: Graduate School at Shenzhen, Tsinghua University
    Inventors: Xiangyuan Zheng, Yu Lei, Daoyi Chen, Yi Li
  • Publication number: 20200059092
    Abstract: An ESD protection circuit includes at least two unidirectional conduction units arranged between an IO node of an integrated circuit and a positive voltage node, where a first connection node is between the at least two unidirectional conduction units; at least two unidirectional conduction units arranged between the IO node and a negative voltage node, where a second connection node is between the at least two unidirectional conduction units; and a voltage tracking circuit. The input of the voltage tracking circuit is electrically connected to the IO node and the output of the voltage tracking circuit is electrically connected to at least one of the first connection end and the second connection end. By reducing the voltage difference between the IO node and the first connection end or between the IO node and the second connection end, the parasite capacitance associated with the unidirectional conduction unit can be reduced.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 20, 2020
    Inventors: Hsiang-Yu LEE, Shang CHIN, Ping-Tsun LIN, Chia-Cheng LEI, Yu-Chieh LIN