Patents by Inventor Yu-Lien Huang

Yu-Lien Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167192
    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
    Type: Application
    Filed: February 10, 2021
    Publication date: June 3, 2021
    Inventors: Yu-Lien Huang, Tung Ying Lee
  • Publication number: 20210111282
    Abstract: A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.
    Type: Application
    Filed: November 30, 2020
    Publication date: April 15, 2021
    Inventors: Yu-Lien Huang, Tung Ying Lee, Winnie Chen
  • Patent number: 10971594
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Patent number: 10937877
    Abstract: Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10930784
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • Publication number: 20210050247
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Patent number: 10923566
    Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes a substrate and an annular nanowire disposed over the substrate.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Lien Huang, Yung-Ta Li, Meng-Ku Chen
  • Publication number: 20210020642
    Abstract: The present disclosure provides example embodiments relating to conductive features, and methods of forming the conductive features, that have differing dimensions. In an embodiment, a structure includes a substrate, a dielectric layer over the substrate, and first and second conductive features through the dielectric layer to first and second source/drain regions, respectively, on the substrate. The first conductive feature has a first length along a longitudinal axis of the first conductive feature and a first width perpendicular to the first length. The second conductive feature has a second length along a longitudinal axis of the second conductive feature and a second width perpendicular to the second length. The longitudinal axis of the first conductive feature is aligned with the longitudinal axis of the second conductive feature. The first width is greater than the second width, and the first length is less than the second length.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Inventor: Yu-Lien Huang
  • Patent number: 10867842
    Abstract: A method includes forming a first hard mask layer and a second hard mask layer over the first hard mask layer, and forming a tri-layer including a bottom layer, a middle layer, and a patterned upper layer. The method further includes etching the middle layer to extend an opening in the patterned upper layer into the middle layer, wherein the opening has a first portion in the middle layer, and the first portion has a first top width and a first bottom width smaller than the first top width; etching the bottom layer to extend the opening into the bottom layer; and etching the second hard mask layer to extend the opening into the second hard mask layer. The opening has a second portion in the second hard mask layer, and the second portion has a second top width and a second bottom width smaller than the second top width.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng Wang, Yu-Lien Huang
  • Patent number: 10854749
    Abstract: A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Winnie Chen
  • Patent number: 10840126
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Publication number: 20200357915
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Yu-Lien HUANG, Meng-Chun CHANG
  • Publication number: 20200343351
    Abstract: Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventor: Yu-Lien Huang
  • Publication number: 20200335390
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a second mask layer over the first mask layer, patterning the second mask layer, forming a third mask layer over the patterned second mask layer, patterning the third mask layer, etching the first mask layer using both the patterned second mask layer and the patterned third mask layer as a combined etch mask, removing the patterned third mask layer to expose a portion of the first mask layer, performing a trim process on the exposed portion of the first mask layer, and etching the target layer using the first mask layer to form openings in the target layer.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Inventor: Yu-Lien Huang
  • Publication number: 20200328291
    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 15, 2020
    Inventors: Yu-Lien Huang, Tung Ying Lee
  • Publication number: 20200321468
    Abstract: A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chun-Hsiang Fan
  • Patent number: 10797058
    Abstract: The present disclosure provides example embodiments relating to conductive features, and methods of forming the conductive features, that have differing dimensions. In an embodiment, a structure includes a substrate, a dielectric layer over the substrate, and first and second conductive features through the dielectric layer to first and second source/drain regions, respectively, on the substrate. The first conductive feature has a first length along a longitudinal axis of the first conductive feature and a first width perpendicular to the first length. The second conductive feature has a second length along a longitudinal axis of the second conductive feature and a second width perpendicular to the second length. The longitudinal axis of the first conductive feature is aligned with the longitudinal axis of the second conductive feature. The first width is greater than the second width, and the first length is less than the second length.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10784106
    Abstract: A method includes etching a portion of a semiconductor material between isolation regions to form a trench, forming a semiconductor seed layer extending on a bottom surface and sidewalls of the trench, etching-back the first semiconductor seed layer until a top surface of the semiconductor seed layer is lower than top surfaces of the isolation regions, performing a selective epitaxy to grow a semiconductor region from the semiconductor seed layer, and forming an additional semiconductor region over the semiconductor region to fill the trench.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, De-Wei Yu
  • Patent number: 10727347
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lien Huang, Meng-Chun Chang
  • Patent number: 10714578
    Abstract: Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Lien Huang