Patents by Inventor Yu-Lien Huang

Yu-Lien Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161797
    Abstract: An integrated circuit (IC) device includes memory cells each including first through fourth memory elements. The first memory element is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line. The second memory element is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor. The first and second memory elements are arranged in a first row along the first axis. The third memory element is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor electrically coupled to the first conductor. The fourth memory element is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line. The third and fourth memory elements are arranged, along the first axis, in a second row spaced from the first row along an axis transverse to the first axis.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Bo-Feng YOUNG, Yu-Ming LIN, Shih-Lien Linus LU, Han-Jong CHIA, Sai-Hooi YEONG, Chia-En HUANG, Yih WANG
  • Patent number: 11978670
    Abstract: A method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. The second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Lien Huang
  • Publication number: 20240145597
    Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu, Yun-Min Chang
  • Publication number: 20240113206
    Abstract: A method includes forming a first multilayer interconnection structure over a carrier substrate. A first interlayer dielectric (ILD) layer is deposited over the first multilayer interconnection structure. A first source/drain contact is formed in the first ILD layer. After forming the first source/drain contact, a semiconductive layer is formed over the first source/drain contact and the first ILD layer. The semiconductive layer is patterned to form a semiconductor fin over the first source/drain contact. A gate structure is formed across the semiconductor fin. The semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact. First and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Lien HUANG
  • Publication number: 20240105516
    Abstract: A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure and the fins. The spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. A source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. A device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. An epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 28, 2024
    Inventor: Yu-Lien Huang
  • Patent number: 11942479
    Abstract: A device includes a channel layer, a gate structure, a source/drain epitaxial structure, and a gate via. The gate structure wraps around the channel layer. The gate structure includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The source/drain epitaxial structure is adjacent the gate structure and is electrically connected to the channel layer. The gate via is under the gate structure and is in contact with a bottom surface of the gate electrode.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Lien Huang
  • Publication number: 20240096696
    Abstract: Provided are conductive structures located within dielectric material, and methods for fabricating such structures and devices. An exemplary method includes providing a substrate having a conductive feature in a first dielectric layer; depositing a second dielectric layer over the conductive feature and the first dielectric layer; etching the second dielectric layer to form a cavity through the second dielectric layer, wherein the cavity has a bottom with a convex profile; depositing a barrier layer along the bottom of the cavity; and depositing a conductive material in the cavity to form a structure electrically connected to the conductive feature.
    Type: Application
    Filed: January 18, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Wei Hsiang Chan
  • Patent number: 11935920
    Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
  • Publication number: 20240087960
    Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Fu-Sheng LI, Tsai-Jung HO, Bor Chiuan HSIEH, Guan-Xuan CHEN, Guan-Ren WANG
  • Publication number: 20240087890
    Abstract: A method includes depositing a photoresist layer over a target layer, the photoresist layer comprising an organometallic material; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation; developing the exposed photoresist layer to form a photoresist pattern; forming a spacer on a sidewall of the photoresist pattern; removing the photoresist pattern; after removing the photoresist pattern, patterning the target layer through the spacer.
    Type: Application
    Filed: August 26, 2022
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Chih-Cheng LIU, Tze-Liang LEE
  • Patent number: 11916147
    Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu, Yun-Min Chang
  • Patent number: 11915787
    Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Feng Young, Yu-Ming Lin, Shih-Lien Linus Lu, Han-Jong Chia, Sai-Hooi Yeong, Chia-En Huang, Yih Wang
  • Publication number: 20240055525
    Abstract: A method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a first recess between the gate spacers, forming a source/drain contact in the first ILD layer, and forming a second interlayer dielectric (ILD) layer to fill in the first recess between the gate spacers and over the source/drain contact.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Tze-Liang LEE, Jr-Hung LI, Chi-Hao CHANG, Hao-Yu CHANG, Pei-Yu CHOU
  • Patent number: 11901452
    Abstract: A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Winnie Chen
  • Patent number: 11888064
    Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: January 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
  • Publication number: 20240021476
    Abstract: In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.
    Type: Application
    Filed: January 6, 2023
    Publication date: January 18, 2024
    Inventors: Yu-Lien Huang, Tze-Liang Lee, Jr-Hung Li, Chun-Kai Chen
  • Publication number: 20240006534
    Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 4, 2024
    Inventors: Ching-Feng Fu, Guan-Ren Wang, Yun-Min Chang, Yu-Lien Huang
  • Patent number: 11855186
    Abstract: A method includes forming a first multilayer interconnection structure over a carrier substrate. A first interlayer dielectric (ILD) layer is deposited over the first multilayer interconnection structure. A first source/drain contact is formed in the first ILD layer. After forming the first source/drain contact, a semiconductive layer is formed over the first source/drain contact and the first ILD layer. The semiconductive layer is patterned to form a semiconductor fin over the first source/drain contact. A gate structure is formed across the semiconductor fin. The semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact. First and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Lien Huang
  • Patent number: 11854897
    Abstract: A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure and the fins. The spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. A source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. A device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. An epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 11854814
    Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu