Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Abstract: Various semiconductor techniques described herein enable reductions in one or more sizes of a fin field-effect transistor (finFET) and/or increasing one or more sizes of a finFET. In various implementations described herein, a material may be used to reduce the one or more x-direction sizes of the finFET by selective deposition while enabling the one or more y-direction sizes of the finFET to be increased or enlarged by etching. The x-direction size of a source or drain of the finFET, the x-direction size of an active region of the finFET, and/or the x-direction size of a polysilicon region of the finFET may be increased by selective deposition of a boron nitride (BxNy), a boron carbide (BxC), a boron oxide (BxOy) (e.g., boric oxide (B2O3), a fluorocarbon (CxFy) polymer, and/or another material.

Abstract: A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.

Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

Abstract: An interconnection structure includes a first conductive feature disposed in a dielectric material, a first etch stop layer disposed over the dielectric material, a first dielectric layer disposed over the first etch stop layer, and a second conductive feature extending through the first dielectric layer and the first etch stop layer and in electrical contact with the first conductive feature. The first etch stop layer includes a boron-based layer, and an oxygen-rich boron-containing layer in contact with the boron-based layer.

Abstract: Embodiments of the present disclosure relates to a semiconductor device structure, including a first gate dielectric layer having a top surface and a corner surface, wherein a highest point of the top surface of the first gate dielectric layer is at a first elevation. The semiconductor device structure includes a first gate electrode layer having a top surface, wherein a highest point of the top surface of the first gate electrode layer is at a second elevation higher than the first elevation. The semiconductor device structure includes a first dielectric cap layer in contact with the top surface and the corner surface of the first gate dielectric layer. The first dielectric cap layer is also in contact with the top surface of the first gate electrode layer. The semiconductor device structure includes a first gate spacer in contact with the first dielectric cap layer and the first gate dielectric layer.

Abstract: A semiconductor structure includes at least a fin structure, a gate structure over the fin structure, a connecting structure, a first dielectric structure over the gate structure, and a second dielectric structure. The fin structure extends in a first direction, and the gate structure extends in a second direction different from the first direction. The connecting structure is disposed over the fin structure and isolated from the gate structure. The second dielectric structure extends in the first direction. The first dielectric structure and the second dielectric structure include a same material. A top surface of the first dielectric structure and a top surface of the second dielectric structure are substantially aligned with each other.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Abstract: Various semiconductor techniques described herein enable reductions in one or more sizes of a fin field-effect transistor (finFET) and/or increasing one or more sizes of a finFET. In various implementations described herein, a material may be used to reduce the one or more x-direction sizes of the finFET by selective deposition while enabling the one or more y-direction sizes of the finFET to be increased or enlarged by etching. The x-direction size of a source or drain of the finFET, the x-direction size of an active region of the finFET, and/or the x-direction size of a polysilicon region of the finFET may be increased by selective deposition of a boron nitride (BxNy), a boron carbide (BxC), a boron oxide (BxOy) (e.g., boric oxide (B2O3), a fluorocarbon (CxFy) polymer, and/or another material.

Abstract: A method includes forming fins extending over a semiconductor substrate; forming a photoresist structure over the fins; patterning a serpentine cut pattern in the photoresist structure to form a cut mask, wherein the serpentine cut pattern extends over the fins, wherein the serpentine cut pattern includes alternating bridge regions and cut regions, wherein each cut region extends in a first direction, wherein each bridge region extends between adjacent cut regions in a second direction, wherein the second direction is within 30° of being orthogonal to the first direction; and performing an etching process using the cut mask as an etching mask.

Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.

Abstract: Methods of forming improved dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a transistor structure on a semiconductor substrate; a first dielectric layer on the transistor structure; a second dielectric layer on the first dielectric layer, the second dielectric layer having a nitrogen concentration greater than a nitrogen concentration of the first dielectric layer; a first conductive structure extending through the second dielectric layer and the first dielectric layer, the first conductive structure being electrically coupled to a first source/drain region of the transistor structure, a top surface of the first conductive structure being level with a top surface of the second dielectric layer; and a second conductive structure physically and electrically coupled to the first conductive structure, a bottom surface of the second conductive structure being a first distance below the top surface of the second dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes forming a source/drain region on a semiconductor fin. The source/drain region is adjacent to a dummy gate. The method further includes forming a first dielectric layer over the source/drain region and the dummy gate. The first dielectric layer has a dielectric constant of 3.5 or less. The first dielectric layer may include boron nitride or silicon dioxide with Si-CH3 bonds.

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming fins from a substrate, forming a gate stack over portions of the fins, forming an epitaxial source/drain region adjacent the gate stack, depositing a dielectric layer over the epitaxial source/drain region, forming an opening in the dielectric layer, and forming a gapfill in the opening in a bottom-up fashion. The gapfill includes Si or W. The method further includes forming a conductive feature over the epitaxial source/drain region and replacing the gapfill with a dielectric material.

Abstract: A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.

Abstract: A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line.

Abstract: A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.

Abstract: The method for forming a semiconductor device includes forming a gate structure over a substrate; forming a plurality of source/drain structures in the substrate and on opposite sides of the gate structure; forming a source/drain contact on one of the plurality of source/drain structures; etching back the source/drain contact; forming a protective structure over the etched back source/drain contact; forming a dielectric layer over the gate structure and the protective structure; etching the dielectric layer to form an opening that exposes the gate structure and the protective structure; selectively depositing a capping material on the protective structure; after selectively depositing the capping material, forming a gate contact in the opening.