Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.

Abstract: A detection device, including a light-emitting component, a light-detecting component, at least one reflective optical film element, and a control unit, is provided. The light-emitting component is used for providing an excitation beam, wherein a part of the excitation beam whose dominant wavelength falls within an excitation wavelength band generates a fluorescence beam after passing through a test specimen. The light-detecting component is used for receiving a part of the fluorescence beam whose dominant wavelength falls within a detection wavelength band. The control unit is coupled to the at least one reflective optical film element. The control unit controls the at least one reflective optical film element to filter out a part of a wavelength band of an incident beam. The incident beam is at least one of the excitation beam and the fluorescence beam. A detection method of the detection device is also provided.

Abstract: Systems and methods for a flexible Power Supply Unit (PSU) bay are described. In some embodiments, a chassis may include a surface and a PSU adaptor disposed on the surface, the PSU adaptor comprising a tab having a stopper coupled thereto, where the stopper is configured to: (a) resist movement, bending, or deformation of a board perpendicularly disposed with respect to the surface upon insertion of a first PSU into a PSU cage, and (b) move downward upon insertion of a second PSU into the PSU cage.

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

Abstract: A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

Abstract: A detection device includes a light emitting element, an accommodation frame, a light detector, and a movable light splitter. The light emitting element provides an excitation beam. The accommodation frame accommodates an object under test, and a portion of the excitation beam whose dominant light emitting wavelength falls within a first waveband range forms a fluorescent beam after passing through the object under test. The light detector receives a portion of the fluorescent beam whose dominant light emitting wavelength falls within a second waveband range. The movable light splitter forms a plurality of sub-beams from an incident beam. The sub-beams have respectively different dominant light emitting wavelengths and exits at different emitting angles. The incident beam is at least one of the excitation beam and the fluorescent beam.

Abstract: In various embodiments, methods and systems for implementing distributed data object management are provided. The distributed data object management system includes a local metadata-consensus information store and one or more remote metadata-consensus information stores for metadata-consensus information and a local data store and one or more remote data stores for erasure coded fragments. For a write operation, corresponding metadata writes and data writes are performed in parallel using a metadata write path and a data write path, respectively, when writing to the local metadata-consensus information store and the one or more remote metadata-consensus information stores and the local data store and the one or more remote data stores. And, for a read operation, corresponding metadata reads and data reads are performed in parallel using a metadata read path and a data read path, respectively, when reading from the metadata-consensus information stores and the data stores.

Abstract: A detection light source module and a detection device are provided. The detection light source module includes a light emitting component, a light shape adjusting component, and a single band pass filter. The light emitting component is adapted to provide a light beam. The light shape adjusting component is located on a transmission path of the light beam and is adapted to adjust a light shape of the light beam. The light beam forms a strip lighting region through the light shape adjusting component, wherein the strip lighting region has a plurality of sub-lighting regions. The sub-lighting regions have the same size and do not overlap each other. The single band pass filter is located on the transmission path of the light beam and is located between the light emitting component and the light shape adjusting component.

Abstract: Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction.

Abstract: An information handling system includes a bracket in physical contact with a server compute module. The bracket includes an adjustable guide that can rotate between a first position and a second position within the bracket. The adjustable guide is in the first position in response to a first peripheral card being inserted within the bracket, and is in the second position in response to a second peripheral card being inserted within the bracket.

Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.

Abstract: Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction.

Abstract: An electrochemical extended-gate transistor (EET) system is provided, the system includes: a field effect transistor (FET), having a gate, a source, and a drain; a potentiostat, having a working electrode, a counter electrode, and a reference electrode; wherein the working electrode is coupled with a detection region, and the counter electrode is coupled with the gate; wherein the detection region, the gate, and the reference electrode are arranged in an ion fluid; wherein the potentiostat is configured to generate redox in the ion fluid by an electrochemical method to detect the target. A method for detecting targets are used to such system.

Abstract: In various embodiments, methods and systems for implementing distributed data object management are provided. The distributed data object management system includes a distributed storage system having a local metadata-consensus information store in and one or more remote metadata-consensus information stores. A metadata-consensus information store is configured to store metadata-consensus information. The metadata-consensus information corresponds to erasure coded fragments of a data object and instruct on how to manage the erasure coded fragments. The distributed storage system further includes a local data store and one or more remote data stores for the erasure coded fragments. The distributed data object management system includes a distributed data object manager for operations including, interface operations, configuration operations, write operations, read operations, delete operations, garbage collection operations and failure recovery operations.

Abstract: A screw may include a head, a threaded cylindrical shaft mechanically coupled to the head such that an axis of the threaded cylindrical shaft extends from the head, and a plurality of substantially spaced serration features formed proximate to where the head is mechanically coupled to the threaded cylindrical shaft, each of the plurality of substantially spaced serration features mechanically coupled to the head and threaded cylindrical shaft. Each serration feature may include a displacer mechanically coupled to the head and the threaded cylindrical shaft and configured to, when the screw is driven into a receptacle for receiving the screw via a countersink, displace material of the countersink and an undercut mechanically coupled to the head and the threaded cylindrical shaft and configured to engage with the countersink in order to prevent the screw from disengaging from the countersink and the receptacle due to a mechanical force upon the screw.

Abstract: In various embodiments, methods and systems for implementing distributed data object management are provided. The distributed data object management system includes a distributed storage system having a local metadata-consensus information store in and one or more remote metadata-consensus information stores. A metadata-consensus information store is configured to store metadata-consensus information. The metadata-consensus information corresponds to erasure coded fragments of a data object and instruct on how to manage the erasure coded fragments. The distributed storage system further includes a local data store and one or more remote data stores for the erasure coded fragments. The distributed data object management system includes a distributed data object manager for operations including, interface operations, configuration operations, write operations, read operations, delete operations, garbage collection operations and failure recovery operations.

Abstract: An information handling system includes a bracket in physical contact with a server compute module. The bracket includes an adjustable guide that can rotate between a first position and a second position within the bracket. The adjustable guide is in the first position in response to a first peripheral card being inserted within the bracket, and is in the second position in response to a second peripheral card being inserted within the bracket.

Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.