Patents by Inventor Yu-Lin Yang

Yu-Lin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130292813
    Abstract: A multi-chip flip chip package includes multiple dies. Each die comprises several pads for coupling with pads of the other die and for coupling with pins of the multi-chip flip chip package through conducting elements. A dielectric element is positioned between the dies and the conducting elements, and positioned between the dies for providing the electrical insulation. The dies and the conducting elements between the dies are coated with a packaging element for preventing physical damage and corrosion.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 7, 2013
    Applicant: Richtek Technology Corporation
    Inventor: Yu-Lin YANG
  • Patent number: 8097952
    Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: January 17, 2012
    Assignee: Richtek Technology Corp.
    Inventor: Yu-Lin Yang
  • Publication number: 20110221047
    Abstract: A flip chip package structure includes a chip placed under a lead frame, a bump on the upper surface of the chip that is electrically connected to the lead of the lead frame, and a backside metal on the lower surface of the chip that is exposed outside an encapsulant encapsulating the chip and a portion of the lead frame.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 15, 2011
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventors: YU-LIN YANG, LIH-MING DOONG
  • Patent number: 7960213
    Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 14, 2011
    Assignee: Richtek Technology Corp.
    Inventor: Yu-Lin Yang
  • Publication number: 20100129962
    Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
    Type: Application
    Filed: January 26, 2010
    Publication date: May 27, 2010
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventor: YU-LIN YANG
  • Publication number: 20100124801
    Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
    Type: Application
    Filed: January 26, 2010
    Publication date: May 20, 2010
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventor: YU-LIN YANG
  • Publication number: 20100123255
    Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
    Type: Application
    Filed: January 26, 2010
    Publication date: May 20, 2010
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventor: YU-LIN YANG
  • Publication number: 20100108669
    Abstract: An assembly box structure includes two first side boards and two second side boards. Symmetric protruding portions are outwardly extended from two short sides of the first side boards. Symmetric recession portions are inwardly caved at two sides of a longer edge of the second side board. The protruding portion of one side of the first side board is embedded with the recession portion of the second side board through the two first side boards interlaced and assembled to the two second side boards, thereby rapidly assembling the hollow box body. Side bottom boards are extended from the bottoms of the first and second side boards. A plurality of through holes is arranged according to the proper distance spaced at interval. A plurality of expansion cylinders is at the periphery of the bottom of a bottom board, and corresponds to the through holes of each side bottom board.
    Type: Application
    Filed: July 20, 2009
    Publication date: May 6, 2010
    Inventor: Yu-Lin Yang
  • Publication number: 20090289058
    Abstract: A box assembly includes a plurality of boards connected to each other and each of the boards includes a plurality of first flips on one side thereof and second flips on another side thereof. Each first flip is cooperated with a first slit which opens downward and each second flip is cooperated with a second slit which opens upward. When connecting two boards, the first flips are inserted into the second slits and the second flips are inserted into the first slits. The first and second flips may extend at angle from the boards so as to obtain a polygonal box.
    Type: Application
    Filed: September 4, 2008
    Publication date: November 26, 2009
    Inventor: Yu-Lin Yang
  • Publication number: 20090283896
    Abstract: A semiconductor die has a surface and an active region on the surface. A thick-film coating is applied to the surface of the semiconductor die to cover only a portion or entire of the active region before the semiconductor die is cut from a wafer. The thick-film coating reduces the stress to the semiconductor die. The thick-film coating does not cover the bonding pads of the semiconductor die to avoid influencing the bonding wires bonding to the boding pads.
    Type: Application
    Filed: May 11, 2009
    Publication date: November 19, 2009
    Inventor: Yu-Lin Yang
  • Patent number: 7528495
    Abstract: A chip structure including a substrate, at least one chip bonding pad, a passivation layer, at least one compliant bump, and at least one redistribution conductive trace is provided. The substrate has an active surface whereon the chip bonding pad is disposed. The passivation layer is disposed on the active surface and exposes the chip bonding pad. The compliant bump has a top surface and a side surface. At least part of the compliant bump is disposed on the passivation layer. One end of the redistribution conductive trace is electrically connected to the chip bonding pad and the other end thereof covers part of the side surface and at least part of the top surface of the compliant bump. Therefore, the chip bonding pad of the chip structure can be electrically connected to the corresponding electrical contact of the carrier through the compliant bump and the redistribution conductive trace.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: May 5, 2009
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventor: Yu-Lin Yang
  • Publication number: 20080197507
    Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 21, 2008
    Inventor: Yu-Lin Yang
  • Publication number: 20080012150
    Abstract: A chip structure including a substrate, at least one chip bonding pad, a passivation layer, at least one compliant bump, and at least one redistribution conductive trace is provided. The substrate has an active surface whereon the chip bonding pad is disposed. The passivation layer is disposed on the active surface and exposes the chip bonding pad. The compliant bump has a top surface and a side surface. At least part of the compliant bump is disposed on the passivation layer. One end of the redistribution conductive trace is electrically connected to the chip bonding pad and the other end thereof covers part of the side surface and at least part of the top surface of the compliant bump. Therefore, the chip bonding pad of the chip structure can be electrically connected to the corresponding electrical contact of the carrier through the compliant bump and the redistribution conductive trace.
    Type: Application
    Filed: October 17, 2006
    Publication date: January 17, 2008
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventor: YU-LIN YANG