Abstract: A method includes forming a first conductive pillar on an interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar includes a barrier layer; bonding a first semiconductor device to the first conductive pillar by a first bonding region that includes more inter-metallic compound than solder; and bonding the first semiconductor device to the second conductive pillar by a second bonding region that includes more solder than inter-metallic compound.

Abstract: The present invention provides a novel dielectric filter, which comprises a dielectric body, N+4 through holes, and an end surface metal layer, wherein the end surface metal layer comprises a first metal block, a second metal block, N middle metal blocks, a penultimate metal block, a last metal block, a first metal sideline, a second metal line segment, a third metal line segment, a fourth metal line segment, and a fifth metal line segment; the first metal block, the second metal block, the N middle metal blocks, the penultimate metal block and the last metal block are respectively formed on peripheral sides of a first resonance hole, a second resonance hole, N middle resonance holes, a penultimate resonance hole and a last resonance hole.

Abstract: The present disclosure relates to a system for making or assembling fiber optic connectors that allows a pre-terminated fiber optic cable to be made compatible with any number of different styles or types of fiber optic connectors or fiber optic adapters. A connector core of the system can be used as a stand-alone connector with a small form-factor adapter.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: Circuit design techniques can use a trained predictor to predict key dynamic current metrics (such as peak current, peak time, pulse width and total charge) for a gate in a circuit library, where the predictor has been trained over different combinations of different input transition slews and different output fanout models. A dynamic current model solver can be used for a gate in the cell library to derive waveforms (of current versus time) for the different combinations, and a predictor, such as a neural network, can be trained with the outputs from the solver for the different combinations. The trained predictor can be used in a runtime simulation to solve for the dynamic current demand model of the various gates in a circuit design (such as all of the gates in an integrated circuit).

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions arranged on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Abstract: Semiconductor devices are provided. A semiconductor device includes a power switch, a first power mesh and a second power mesh. The power switch has a first terminal and a second terminal. The first power mesh is directly connected to the first terminal of the power switch. The second power mesh is directly connected to the second terminal of the power switch. The first power mesh includes a first power rail over the power switch and extending in a first direction. The second power mesh includes a second power rail under the power switch and extending in the first direction. The first and second power rails are separated from each other.

Abstract: A laser soldering system using dynamic light spot and a method thereof are provided. A laser module is controlled to radiate toward multi-lens to form a light spot on a soldering target for soldering, and a lens distance between the multi-lens is adjusted to adjust a light spot size. The disclosure may provide multiple heating densities respectively adequate to different soldering status via adjusting the light spot size when using same laser power, so as to improve the soldering quality.

Abstract: A fiber optic and electrical connection system includes a fiber optic cable, a ruggedized fiber optic connector, a ruggedized fiber optic adapter, and a fiber optic enclosure. The cable includes one or more electrically conducting strength members. The connector, the adapter, and the enclosure each have one or more electrical conductors. The cable is terminated by the connector with the conductors of the connector in electrical communication with the strength members. The conductors of the connector electrically contact the conductors of the adapter when the connector and the adapter are mechanically connected. And, the conductors of the adapter electrically contact the conductors of the enclosure when the adapter is mounted on the enclosure.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: The present invention discloses a mobile energy storage internet system. The mobile energy storage internet system comprises distributed energy harvesting devices, mobile cold storage/heat storage devices, an energy system dispatching and monitoring center, and cold supply/heat supply terminals. The distributed energy harvesting devices are used for harvesting industrial waste cold energy/heat energy. The energy system dispatching and monitoring center is used for monitoring the residual energy of the distributed energy harvesting devices and the energy demand of the cold supply/heat supply terminals respectively, and mobilizing the mobile cold storage/heat storage devices to the distributed energy harvesting devices to store residual energy or to the cold supply/heat supply terminals to release the stored residual energy.

Abstract: Provided is a use of nintedanib or a pharmaceutically acceptable salt thereof in preparing a drug for treating tuberculosis. The nintedanib or the pharmaceutically acceptable salt thereof is used in combination with a further anti-tuberculosis drug for treating tuberculosis, or used as an adjuvant drug for the treating tuberculosis, where the further anti-tuberculosis drug is selected from a group consisting of: rifampicin, isoniazid, pyrazinamide, ethambutol, fluoroquinolone, streptomycin, kanamycin, amikacin, capreomycin, sodium para-aminosalicylate, ethionamide, cycloserine, clofazimine, and linezolid.

Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: A method of determining interaction information, an electronic device and a storage medium are provided, which relates to a field of artificial intelligence technology, in particular to a large model, a generative model, an NLP, an intelligent search and other fields. An implementation is to determine a plurality of questioning dimensions according to query information of a subject and historical query information, where each questioning dimension includes a dimension name and a plurality of options; determine a target questioning dimension from the plurality of questioning dimensions according to evaluation values of the plurality of questioning dimensions and whether semantic information of the plurality of questioning dimensions are consistent with semantic information of a query result associated with the query information; and determine the interaction information according to the dimension name and the plurality of options in the target questioning dimension.

Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.

Abstract: A method of forming a semiconductor device includes forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to a doped region. The method further includes forming a via-to-via (V2V) rail which extends in a second direction angled with respect to the first direction, wherein the V2V rail overlaps at least of the first MD contact structure or the third MD contact structure. The method further includes forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail. The method further includes forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.

Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.