Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: Systems and methods for indicating positioning information in wireless communication systems are disclosed. In one aspect, a method includes receiving, by a wireless communication device from a network, network timing error information; and reporting, by the wireless communication device to the network, downlink measurement results and User Equipment (UE) timing error information, wherein, the network timing error information comprises at least one of Transmission and Reception Point (TRP) transmission Timing Error Group (TEG) information and TRP reception TEG information; the UE timing error information comprises at least one of UE transmission TEG information and UE reception TEG information.

Abstract: A data processing method includes: generating a service serial number for a target service according to a preset naming rule; obtaining service data of the target service; obtaining a target data table from a plurality of pre-configured data tables, according to the service serial number; and storing the service data to the target data table.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Memories, memory controllers, and computing systems and their methods of operation are disclosed. In some embodiments, a method of accessing a memory includes accessing a first bit line corresponding to a sense amplifier and accessing a second bit line corresponding to the sense amplifier. In some embodiments, a memory controller includes a second memory configured to store data of a second data type. In some embodiments, a method includes operating a memory in a second mode in response to receiving an input to change the operation of the memory from a first mode to the second mode.

Abstract: Provided are an information transmission method and a relevant device. The method includes: a terminal receiving first signaling and second signaling, where the first signaling is configured for indicating a transmission configuration indication (TCI) state, and the second signaling is configured for triggering a first reference signal indicated in the TCI state; and the terminal determining, according to the first signaling, a target channel or a target signal scheduled by the first signaling, where the target channel or the target signal scheduled by the first signaling uses quasi-co-location (QCL) information corresponding to the first reference signal transmitted before a first symbol or QCL information corresponding to the second signaling transmitted before a first symbol.

Abstract: A display substrate and a manufacturing method and a display device are provided. The display substrate includes: a first electrode pattern, a connecting electrode pattern, a second electrode, and a light-emitting functional layer. The first electrode pattern is located in a display region and includes a plurality of first electrodes spaced apart from each other. The connecting electrode pattern is located in a peripheral region and includes a plurality of connecting electrodes. The second electrode is connected with the connecting electrode pattern, the second electrode and the first electrode pattern being spaced apart from each other. The light-emitting functional layer is located between the first electrode pattern and the second electrode, the connecting electrode pattern surrounds the first electrode pattern, and at least two of the plurality of connecting electrodes are each of a block shape and are spaced apart from each other.

Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

Abstract: This disclosure relates to wireless radio link recovery methods. In various implementations, the method includes determining a beam failure event for a first cell, and transmitting a beam recovery request message on a shared uplink channel when available. In other implementations, the method includes determining that the shared uplink channel is not available for transmitting the beam recovery request message and transmitting a resource request to request allocation of the shared uplink channel via a second cell.

Abstract: A method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. Creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. Creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

Abstract: A display panel includes a drive backplane, a transparent insulating layer and a light-emitting device layer. The drive backplane includes a driving circuit layer, a metal wiring layer, a first insulating layer and a reflective electrode layer. The first insulating layer has first via holes filled with first metal connectors. The reflective electrode layer includes first reflective electrodes respectively connected with the metal wiring layer through the first metal connectors. The light-emitting device layer includes a pixel electrode layer, an organic light-emitting layer and a common electrode layer. The pixel electrode layer includes first pixel electrodes respectively connected with the first reflective electrodes through the connection via holes. A distance between an orthographic projection of the connection via hole on the pixel electrode layer and an edge of the first pixel electrode is not less than a first threshold value.

Abstract: Disclosed are methods of making selective estrogen receptor degraders (SERDs) of Formula A, as well as intermediates thereof, salts thereof including a pharmaceutically acceptable salt, and pharmaceutical compositions thereof: wherein either R1 or R2 is independently Cl, F, —CF3, or —CH3, and the other is H; and R7 is H or PG.

Abstract: Described are a method, system, and computer program product for operating dynamic shadow testing environments for machine-learning models. The method includes generating a shadow testing environment operating at least two transaction services. The method also includes receiving a plurality of transaction authorization requests. The method further includes determining a first percentage associated with a first testing policy of the first transaction service and a second percentage associated with a second testing policy of the second transaction service. The method further includes replicating in the shadow testing environment, in real-time with processing the payment transactions, a first portion of the plurality of transaction authorization requests and a second portion of the plurality of transaction authorization requests.

Abstract: Provided is a display substrate, including: a silicon-based substrate having a display area, a binding area located on one side of the display area, and a trace area located between the display area and the binding area; a trace protection structure is arranged on the silicon-based substrate in the trace area, and a pad assembly is integrated in the silicon-based substrate in the binding area; and a minimum distance between an edge of an orthographic projection of the trace protection structure on the silicon-based substrate and an edge of an orthographic projection of an opening of the pad assembly on the silicon-based substrate is smaller than a maximum size of one subpixel.

Abstract: Provided are CSI feedback and receiving methods, apparatuses, a device, and a storage medium. The method includes: a terminal determines PMI, the PMI includes at least one of: first base vector information, second base vector information, second coefficient amplitude information or phase information; for one transmission layer, a frequency domain resource in one preset frequency domain unit corresponds to one precoding vector, the precoding vector is a linear combination of first base vectors, and weighting coefficients used in the linear combination of the first base vectors are first coefficients; on multiple frequency domain units contained in a CSI feedback band, a vector composed of first coefficients corresponding to a same first base vector is a linear combination of second base vectors, and weighting coefficients used in the linear combination of the second base vectors are second coefficients; and the terminal feeds back CSI containing the PMI to a base station.

Abstract: The system determines whether an orientation of a ferrule was changed between measurements made to the end face geometry of the ferrule. Accordingly, the systems allows confirmation that a ferrule was re-oriented between measurements before calculating any deviations in the measurement tool and applying corrective algorithms. An indication (e.g., alarm, error message, etc.) may be conveyed to the user to properly re-orient the ferrule.