Patents by Inventor Yu Lu

Yu Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11930673
    Abstract: A display panel includes a drive backplane, a transparent insulating layer and a light-emitting device layer. The drive backplane includes a driving circuit layer, a metal wiring layer, a first insulating layer and a reflective electrode layer. The first insulating layer has first via holes filled with first metal connectors. The reflective electrode layer includes first reflective electrodes respectively connected with the metal wiring layer through the first metal connectors. The light-emitting device layer includes a pixel electrode layer, an organic light-emitting layer and a common electrode layer. The pixel electrode layer includes first pixel electrodes respectively connected with the first reflective electrodes through the connection via holes. A distance between an orthographic projection of the connection via hole on the pixel electrode layer and an edge of the first pixel electrode is not less than a first threshold value.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: March 12, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhijian Zhu, Yu Ao, Yunlong Li, Pengcheng Lu, Yuanlan Tian
  • Publication number: 20240080079
    Abstract: Provided are CSI feedback and receiving methods, apparatuses, a device, and a storage medium. The method includes: a terminal determines PMI, the PMI includes at least one of: first base vector information, second base vector information, second coefficient amplitude information or phase information; for one transmission layer, a frequency domain resource in one preset frequency domain unit corresponds to one precoding vector, the precoding vector is a linear combination of first base vectors, and weighting coefficients used in the linear combination of the first base vectors are first coefficients; on multiple frequency domain units contained in a CSI feedback band, a vector composed of first coefficients corresponding to a same first base vector is a linear combination of second base vectors, and weighting coefficients used in the linear combination of the second base vectors are second coefficients; and the terminal feeds back CSI containing the PMI to a base station.
    Type: Application
    Filed: October 30, 2023
    Publication date: March 7, 2024
    Applicant: ZTE Corporation
    Inventors: Hao WU, Yijian CHEN, Guozeng ZHENG, Yong LI, Zhaohua LU, Yu Ngok LI
  • Publication number: 20240077307
    Abstract: The system determines whether an orientation of a ferrule was changed between measurements made to the end face geometry of the ferrule. Accordingly, the systems allows confirmation that a ferrule was re-oriented between measurements before calculating any deviations in the measurement tool and applying corrective algorithms. An indication (e.g., alarm, error message, etc.) may be conveyed to the user to properly re-orient the ferrule.
    Type: Application
    Filed: October 7, 2020
    Publication date: March 7, 2024
    Applicant: COMMSCOPE TECHNOLOGIES LLC
    Inventors: Yu LU, Joseph BLASER, Antonius Bernardus Gerardus BOLHAAR, Paul SCHNEIDER
  • Patent number: 11921329
    Abstract: The present disclosure relates to a system for making or assembling fiber optic connectors that allows a pre-terminated fiber optic cable to be made compatible with any number of different styles or types after optic connectors or fiber optic adapters. The present disclosure also relates to a fiber optic connector having first and second pieces connected to twist-to-engage interface and also including a rotational interlock. The present disclaimer relates to a fiber optic connector having a boot that mounts in multiple different axial positions.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: March 5, 2024
    Assignee: CommScope Technologies LLC
    Inventors: Yu Lu, Ryan Kostecka
  • Patent number: 11924964
    Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: March 5, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lin Hui Chen, Songtao Lu, Chien Te Chen, Yu Ying Tan, Huang Pao Yi, Ching Chuan Hsieh, T. Sharanya Kaminda, Chia-Hsuan Huang
  • Patent number: 11923861
    Abstract: A voltage controlled oscillator (VCO), including: at least one second upper voltage rail; at least one second lower voltage rail; a ring of N cascaded inverters, wherein the set of N cascaded inverters are coupled between the at least one second upper voltage rail and the at least one second lower voltage rail; at least one first frequency band select circuit coupled between first upper voltage rail and the at least one second upper voltage rail; at least one second frequency band select circuit coupled between the at least one second lower voltage rail and first lower voltage rail; at least one first VCO frequency control circuit coupled between the first upper voltage rail and the at least one second upper voltage rail; and at least one second VCO frequency control circuit coupled between the at least one second lower voltage rail and the first lower voltage rail.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: March 5, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Hao Liu, Lejie Lu, Yu Song, Dong Ren
  • Publication number: 20240066635
    Abstract: A laser machining device includes a pulsed laser generator, an accommodation chamber, a bandwidth broadening unit and a pulse compression unit. The pulsed laser generator is configured to emit a pulsed laser. The accommodation chamber has a gas inlet. The bandwidth broadening unit is disposed in the accommodation chamber, and is configured to broaden a frequency bandwidth of the pulsed laser to obtain a broad bandwidth pulsed laser. The pulse compression unit is disposed in the accommodation chamber. The bandwidth broadening unit and the pulse compression unit are arranged in order along a laser propagation path, and the pulse compression unit is configured to compress a pulse duration of the broad bandwidth pulsed laser.
    Type: Application
    Filed: October 5, 2022
    Publication date: February 29, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chi LEE, Bo-Han CHEN, Chih-Hsuan LU, Ping-Han WU, Zih-Yi LI, Shang-Yu HSU
  • Publication number: 20240071656
    Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.
    Type: Application
    Filed: January 13, 2023
    Publication date: February 29, 2024
    Inventors: Chien Hui WU, Yung-Hsien CHANG, Cheng-Yu TUNG, Ming-Hsun LU, Yi-An SHA
  • Publication number: 20240072075
    Abstract: An electronic device including a substrate, a first electrode layer, a photodiode, an insulating layer, a second electrode layer, and a first transparent conductive layer is provided. The first electrode layer is disposed on the substrate. The photodiode is disposed on the first electrode layer and is electrically connected to the first electrode layer. The insulating layer is disposed on the photodiode. The second electrode layer is disposed on the insulating layer and is electrically connected to the photodiode. The first transparent conductive layer is disposed on the insulating layer and contacts the second electrode layer. A manufacturing method of an electronic device is also provided.
    Type: Application
    Filed: July 18, 2023
    Publication date: February 29, 2024
    Applicants: InnoCare Optoelectronics Corporation, Innolux Corporation
    Inventors: Chin-Chi Chen, Ting-Yu Chen, Yi-Ju Tseng, Ji-Zhen Lu
  • Publication number: 20240071849
    Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Jian-You Chen, Kuan-Yu Huang, Li-Chung Kuo, Chen-Hsuan Tsai, Kung-Chen Yeh, Hsien-Ju Tsou, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20240072079
    Abstract: A method for forming an isolation structure includes following operations. A trench is formed in a semiconductor substrate. A first insulating layer covering a bottom and sidewalls of the trench is formed. A charge-trapping layer is formed on the first insulating layer. The trench is filled with a second insulating layer. The charge-trapping layer include a material different from those of the first insulating layer and the second insulating layer.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: TZUNG-YI TSAI, KUO-YU WU, TSE-HUA LU
  • Patent number: 11916091
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Patent number: 11915994
    Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
  • Patent number: 11914277
    Abstract: An illumination system for providing an illumination beam includes red, blue, and green light source modules, a first light combining element, and a light uniforming element. The red light source module includes a first red light emitting element emitting first red light and a second red light emitting element emitting second red light. A peak wavelength of the second red light is greater than a peak wavelength of the first red light. The blue light source module includes a first blue light emitting element emitting first blue light and a second blue light emitting element emitting second blue light. A peak wavelength of the second blue light is less than a peak wavelength of the first blue light. The green light source module generates green light. The first light combining element guides these lights into the light uniforming element, so that the illumination system outputs the illumination beam.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: February 27, 2024
    Assignee: Coretronic Corporation
    Inventors: Hung-Yu Lin, Chi-Fu Liu, Chun-Hsin Lu, Chun-Li Chen
  • Patent number: 11916820
    Abstract: Disclosed are a reference signal configuration method and device, an information transmission method and device, and an information receiving method and device. The reference signal configuration method includes: indicating, by a first communication node, via signaling a resource used by a second communication node for transmitting a reference signal; or predefining, by a first communication node and a second communication node, a resource used by the second communication node for transmitting a reference signal. Further disclosed are a storage medium and a processor.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: February 27, 2024
    Assignee: ZTE CORPORATION
    Inventors: Yuxin Wang, Shujuan Zhang, Zhaohua Lu, Yu Ngok Li, Chuangxin Jiang
  • Publication number: 20240061182
    Abstract: A retention and protection device holds one or more envelope attachments to a connector core. The envelope attachment may be removed from the device and installed upon the connector core to convert the connector core into a different type of connector to mate with or within a different style of connector or port. The device is a combination of features including a clasp for attachment to the connector core, such as by residing within a recessed valley of a strain relief boot of the connector core. One or more lanyards may be provided. Each lanyard has a first end attached to the clasp and a second end with a fitting. The fitting is structurally dimensioned to removably hold an envelope attachment and prevent dust from entering one end of the envelope attachment. Once removed from the fitting, the envelope attachment is structurally compatible to attach to the connector core.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: Yu LU, Ryan M. Kostecka
  • Publication number: 20240061183
    Abstract: The present disclosure relates to a ferrule boot that provides a pitch conversion from fiber ribbon having a first pitch (e.g., about 200 microns) to a multi-fiber ferrule having fiber openings arranged at a second pitch larger than the first pitch (e.g., about 250 microns). The ferrule boot may also function as a tool for inserting pitch converted optical fibers into the multi-fiber ferrule.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: Paige E. CANZONIERI, Richard S. TIEV, Jaime GONZALEZ BATISTA, Scott L CARLSON, Yu LU, Bruce OGREN, Chinmay M. BENDALE, Joseph Fredrick COWDERY, Seth C. TACCOLA
  • Patent number: 11907633
    Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Patent number: 11904257
    Abstract: A system for increasing the extraction of an active ingredient includes a vacuum quick-dissolving tank, a mixer, a solid-liquid separator, and a homogenizer. The vacuum quick-dissolving tank receives a sample. The mixer is connected to the vacuum quick-dissolving tank, and provides an aqueous solvent to be mixed with the sample. Heating, cooling, stirring, and vacuuming in the vacuum quick-dissolving tank make the sample dissolve and emulsify repeatedly between the vacuum quick-dissolving tank and the mixer to produce a mixture, which is output by the vacuum quick-dissolving tank. The solid-liquid separator receives the mixture output from the vacuum quick-dissolving tank for solid-liquid separation, and outputs an isolated sample liquid. The homogenizer receives the sample liquid output from the solid-liquid separator, performs high-pressure homogenization to obtain an extract liquid containing an active ingredient, and outputs the extract liquid.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: February 20, 2024
    Assignee: TCI CO., LTD.
    Inventors: Yung-Hsiang Lin, Chien-Yu Lu, Jin-Jia Wang
  • Patent number: D1015503
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: February 20, 2024
    Assignee: Global Outdoors, Inc.
    Inventors: Michael Robert Horsfield, Yu Lu, Jiayong Feng