Abstract: A fan assembly including a base, a fan, a light-emitting unit, and a lighting effect component is provided. The fan is rotatably disposed above the base, and includes a central part and multiple blades extending outwards from the central part, and each of the blades has a top surface away from the base. The light-emitting unit is disposed on the base and located between the base and the central part of the fan. The lighting effect component is disposed on the base and surrounds the light-emitting unit. A projection of the lighting effect component projected onto the base is greater than a projection of the fan projected onto the base. A height of the lighting effect component protruding from the base is less than a distance between the top surface of one of the blades and the base. The lighting effect component includes an inclined inner surface.

Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a gate structure, a source doped region, a drain doped region, source silicide patterns, and drain silicide patterns. The gate structure is disposed on the semiconductor substrate. The source doped region and the drain doped region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction, respectively. The source silicide patterns are disposed on the source doped region. The source silicide patterns are arranged in a second direction and separated from one another. The drain silicide patterns are disposed on the drain doped region. The drain silicide patterns are arranged in the second direction and separated from one another. The source silicide patterns and the drain silicide patterns are arranged misaligned with one another in the first direction.

Abstract: A semiconductor device includes a substrate and a first active region on a first side of the substrate. The semiconductor device further includes a first gate structure surrounding a first portion of the first active region. The semiconductor device further includes a second active region on a second side of the substrate, wherein the second side is opposite the first side. The semiconductor device further includes a second gate structure surrounding a first portion of the second active region. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Abstract: This disclosure relates to picolinamides of Formula I and their use as fungicides.

Abstract: Metallization structure for an integrated circuit. In one embodiment, an integrated circuit includes a metal-to-diffusion (MD) layer disposed over an active region of a cell, gates disposed over the active region of the cell, and a first metallization layer including M0 tracks disposed over the MD layer and the gates. The integrated circuit further includes a second metallization layer including M1 tracks disposed over the first metallization layer. The M1 tracks include first M1 tracks each having a first predetermined distance from an edge of the cell and second M1 tracks each having a second predetermined distance from the edge of the cell, wherein the first MI tracks are longer than the second M1 tracks.

Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.

Abstract: The present disclosure provides a fluorescently-traceable amino acid derivative and a preparation method and use thereof, and belongs to the technical field of biomedicine. In the present disclosure, an amino acid skeleton of the amino acid derivative is modified mainly by a fluorescently-traceable functional group. 4-chloro-7-nitro-2,1,3-benzoxadiazole (NBD-Cl) has low polarity and strong fluorescence, and can be used to modify an N-terminal of the amino acid skeleton to conduct subcellular imaging. Moreover, the NBD-Cl has a relatively small volume, lacks reaction orthogonality, and causes little interference with biochemical reactions of the organism itself. The results of examples show that the fluorescently-traceable amino acid derivative has a desirable biological activity and can be fluorescently traced in vivo and in vitro.

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

Abstract: An integrated circuit including a first cell and a second cell. The first cell includes a first plurality of active areas that extend in a first direction and a first plurality of gates that extend in a second direction that crosses the first direction, the first cell having first cell edges defined by breaks in the first plurality of gates. The second cell includes a second plurality of active areas that extend in the first direction and a second plurality of gates that extend in the second direction, the second cell having second cell edges defined by breaks in the second plurality of gates. Each of the second plurality of active areas is larger than each of the first plurality of active areas and the first cell is adjacent the second cell such that the first cell edges align with the second cell edges.

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: A semiconductor device includes an application processor (AP) die and a memory die directly bonded to the AP die. The memory die includes a substrate, a non-volatile memory structure on the substrate, and at least one trench capacitor in the substrate.

Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.

Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

Abstract: A method of forming a semiconductor device, includes forming an active region; forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to the active region; forming a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, overlaps at least the first MD contact structure and the third MD contact structures; forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail; and forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.

Abstract: Disclosed are methods of making selective estrogen receptor degraders (SERDs) of Formula A, as well as intermediates thereof, salts thereof including a pharmaceutically acceptable salt, and pharmaceutical compositions thereof: wherein either R1 or R2 is independently Cl, F, —CF3, or —CH3, and the other is H; and R7 is H or PG.

Abstract: A digital circuit in a baseband receiver to compensate for the IQ mismatch by aligning the amplitude of ? with {tilde over (Q)} and by aligning the phase of {tilde over (Q)} to be 90 degrees away from ?.

Abstract: Provided is a scooter radar detection system for a scooter, including: a control module for controlling operation of the scooter radar detection system; two detection radars flanking a license plate, facing the rear of the scooter, and being in signal connection with the control module; two flash alert units disposed at rear-view mirrors on two sides of the scooter, respectively, and being in signal connection with the control module; and a vibration alert module disposed below a seat and being in signal connection with the control module.