Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

Abstract: A plating membrane includes a support structure extending radially outward from a nozzle that is to direct a flow of a plating solution toward a wafer. The plating membrane also includes a frame, supported by the support structure, having an inner wall that is angled outward from the nozzle. The outward angle of the inner wall relative to the nozzle directs a flow of plating solution from the nozzle in a manner that increases uniformity of the flow of the plating solution toward the wafer, reduces the amount of plating solution that is redirected inward toward the center of the plating membrane, reduces plating material voids in trenches of the wafer (e.g., high aspect ratio trenches), and/or the like.

Abstract: An image sensor with high quantum efficiency is provided. In some embodiments, a semiconductor substrate includes a non-porous semiconductor layer along a front side of the semiconductor substrate. A periodic structure is along a back side of the semiconductor substrate. A high absorption layer lines the periodic structure on the back side of the semiconductor substrate. The high absorption layer is a semiconductor material with an energy bandgap less than that of the non-porous semiconductor layer. A photodetector is in the semiconductor substrate and the high absorption layer. A method for manufacturing the image sensor is also provided.

Abstract: An image sensor with high quantum efficiency is provided. In some embodiments, a semiconductor substrate includes a non-porous semiconductor layer along a front side of the semiconductor substrate. A periodic structure is along a back side of the semiconductor substrate. A high absorption layer lines the periodic structure on the back side of the semiconductor substrate. The high absorption layer is a semiconductor material with an energy bandgap less than that of the non-porous semiconductor layer. A photodetector is in the semiconductor substrate and the high absorption layer. A method for manufacturing the image sensor is also provided.

Abstract: A plating membrane includes a support structure extending radially outward from a nozzle that is to direct a flow of a plating solution toward a wafer. The plating membrane also includes a frame, supported by the support structure, having an inner wall that is angled outward from the nozzle. The outward angle of the inner wall relative to the nozzle directs a flow of plating solution from the nozzle in a manner that increases uniformity of the flow of the plating solution toward the wafer, reduces the amount of plating solution that is redirected inward toward the center of the plating membrane, reduces plating material voids in trenches of the wafer (e.g., high aspect ratio trenches), and/or the like.

Abstract: A semiconductor device includes an ultra-thick metal (UTM) structure. The semiconductor device includes a passivation layer including a first passivation oxide. The first passivation oxide includes an unbias film and a first bias film, where the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film. The passivation layer includes a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film. The passivation layer includes a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.

Abstract: A method is provided that includes forming a first metal layer of a seal structure over a micro-electromechanical system (MEMS) structure and over a channel formed through the MEMS structure to an integrated circuit of a semiconductor structure. The first metal layer is formed at a first temperature. The method includes forming a second metal layer over the first metal layer. The second metal layer is formed at a second temperature less than the first temperature. The method includes performing a first cooling process to cool the semiconductor structure.

Abstract: One or more semiconductor processing tools may deposit a contact etch stop layer on a substrate. In some implementations, the contact etch stop layer is comprised of less than approximately 12 percent hydrogen. Depositing the contact etch stop layer may include depositing contact etch stop layer material at a temperature of greater than approximately 600 degrees Celsius, at a pressure of greater than approximately 150 torr, and/or with a ratio of at least approximately 70:1 of NH3 and SiH4, among other examples. The one or more semiconductor processing tools may deposit a silicon-based layer above the contact etch stop layer. The one or more semiconductor processing tools may perform an etching operation into the silicon-based layer until reaching the contact etch stop layer to form a trench isolation structure.

Abstract: A metal-insulator-metal (MIM) device may include a first metal layer. The MIM device may include an insulator stack on the first metal layer. The insulator stack may include a first high dielectric constant (high-K) layer on the first metal layer. The insulator stack may include a low dielectric constant (low-K) layer on the first high-K layer. The insulator stack may include a second high-K layer on the low-K layer. The MIM device may include a second metal layer on the insulator stack.

Abstract: A semiconductor device includes an ultra-thick metal (UTM) structure. The semiconductor device includes a passivation layer including a first passivation oxide. The first passivation oxide includes an unbias film and a first bias film, where the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film. The passivation layer includes a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film. The passivation layer includes a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.

Abstract: A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.

Abstract: A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.

Abstract: A semiconductor processing system is provided to form a capacitor dielectric layer in a metal-insulator-metal capacitor. The semiconductor processing system includes a precursor tank configured to generate a precursor gas from a metal organic solid precursor, a processing chamber configured to perform a plasma enhanced chemical vapor deposition, and at least one buffer tank between the precursor tank and the processing chamber. The at least one buffer tank is coupled to the precursor tank via a first pipe and coupled to the processing chamber via a second pipe.

Abstract: A semiconductor processing system is provided to form a capacitor dielectric layer in a metal-insulator-metal capacitor. The semiconductor processing system includes a precursor tank configured to generate a precursor gas from a metal organic solid precursor, a processing chamber configured to perform a plasma enhanced chemical vapor deposition, and at least one buffer tank between the precursor tank and the processing chamber. The at least one buffer tank is coupled to the precursor tank via a first pipe and coupled to the processing chamber via a second pipe.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Abstract: A semiconductor device includes an ultra-thick metal (UTM) structure. The semiconductor device includes a passivation layer including a first passivation oxide. The first passivation oxide includes an unbias film and a first bias film, where the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film. The passivation layer includes a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film. The passivation layer includes a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.

Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.