Patents by Inventor Yu-Ming Hsu

Yu-Ming Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230027552
    Abstract: A fluid immersion cooling system includes a fluid tank that contains a layer of a dual-phase coolant fluid and one or more layers of single-phase coolant fluids. The dual-phase and single-phase coolant fluids are immiscible, with the dual-phase coolant fluid having a lower boiling point and higher density than a single-phase coolant fluid. A substrate of an electronic system is submerged in the tank such that high heat-generating components are immersed at least in the layer of the dual-phase coolant fluid. Heat from the components is dissipated to the dual-phase coolant fluid to generate vapor bubbles of the dual-phase coolant fluid. The vapor bubbles rise to a layer of a single-phase coolant fluid that is above the layer of the dual-phase coolant fluid. The vapor bubbles condense to droplets of the dual-phase coolant fluid. The droplets fall down into the layer of the dual-phase coolant fluid.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Applicant: Super Micro Computer, Inc.
    Inventors: Yueh Ming LIU, Yu Hsiang HUANG, Yu Chuan CHANG, Tan Hsin CHANG, Hsiao Chung CHEN, Chia-Wei CHEN, Chih-Ta CHEN, Cheng-Hung LIN, Ming-Te HSU
  • Patent number: 11563088
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 24, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20230020271
    Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11557666
    Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.
    Type: Grant
    Filed: November 22, 2020
    Date of Patent: January 17, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20230008165
    Abstract: A method is provided for sealing a seam in a self-aligned contact (SAC) layer that is disposed on a gate of a semiconductor structure. The method includes depositing a filler in the seam to seal the seam.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Che-Ming HSU
  • Publication number: 20230007281
    Abstract: Video processing methods and apparatuses for processing a current block in a current picture by reference picture resampling include receiving input data of the current block, determining a scaling window of the current picture and a scaling window of a reference picture. The current picture and reference picture may have different scaling window sizes. A ratio between a scaling window width, height, or size of the current picture and a scaling window width, height, or size of the reference picture is constrained to be within a ratio constraint. A reference block is generated from the reference picture according to the ratio, and used to encode or decode the current block.
    Type: Application
    Filed: December 10, 2020
    Publication date: January 5, 2023
    Inventors: Tzu-Der CHUANG, Chih-Wei HSU, Ching-Yeh CHEN, Chia-Ming TSAI, Chun-Chia CHEN, Olena CHUBACH, Lulin CHEN, Yu-Wen HUANG
  • Publication number: 20220416068
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11532712
    Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Lien Huang, Ching-Feng Fu, Guan-Ren Wang, Che-Ming Hsu
  • Publication number: 20220395954
    Abstract: A prognostic and health management system for precision ball grinding machines includes: a detector connected to a first and a second grinding discs; and a central processing module including a determining unit, a historical data recording unit, a timing unit, and an alarm unit. The detector is connected to the determining unit, detects data of the two grinding discs, and sends the data to the determining unit, the determining unit compares data in the historical data recording unit to determine whether the first and second grinding discs are abnormal, if there is an abnormality, the alarm unit releases a warning signal, if the determining unit determines that there is no abnormality, the timing unit records a grinding time of the first and second grinding discs, and based on a comparison of the past records, the alarm unit releases a warning signal after a predetermined time has elapsed.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 15, 2022
    Inventors: Ya-Chen Hsu, Yu-Ming Huang, Yei-Gei Chen, Kuan-Ting Kuo, Shiang-Chi Chen, Po-Hsiu Ko
  • Patent number: 11527448
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: December 13, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Patent number: 11527504
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20220392036
    Abstract: In general, techniques are described regarding fusing or combining frames of image data to generate composite frames of image data. Cameras comprising camera processors configured to perform the techniques are also disclosed. A camera processor may capture multiple frames at various focal lengths. The frames of image data may have various regions of the respective frame in focus, whereas other regions of the respective frame may not be in focus, due to particular configurations of lens and sensor combinations used. The camera processor may combine the frames to achieve a single composite frame having both a first region (e.g., a center region) and a second region (e.g., an outer region) in focus.
    Type: Application
    Filed: May 1, 2020
    Publication date: December 8, 2022
    Inventors: Wen-Chun Feng, Yu-Chen Hsu, Mian Li, Hsuan-Ming Liu
  • Publication number: 20220379433
    Abstract: Provided is a dressing device for a carrier. The dressing device comprises a dresser, a swing arm, a base and at least one damper. A first end and a second end of the swing arm are coupled to the dresser and the base, respectively, and the at least one damper is disposed inside the swing arm. Any axial vibration of the dresser or the swing arm during dressing for the carrier can be compensated or attenuated by the damper in an active manner properly, so as to make the surface of the carrier flatter and more uniform, which not only improves a removal rate of material and a polishing result of the surface in the subsequent chemical mechanical planarization process, but also prolongs the service life of the carrier. The present disclosure further relates to a polishing system for dressing the carrier by using the said dressing device.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 1, 2022
    Inventors: Chao-Chang Chen, Jen-Chieh Li, Cheng-Hsi Chuang, Shih-Chung Hsu, Yu-Tung Tsai, Hsien-Ming Lee, Chun-Chen Chen, Ching-Tang Hsueh
  • Publication number: 20220385889
    Abstract: A method and apparatus for video coding using Intra prediction are disclosed. In one method, a first prediction sample in an immediately right column of the current block and a second prediction sample in an immediately below row of the current block are derived using angular prediction. The first prediction sample and a left column reference sample in the same row as the first prediction sample are interpolated to generate a horizontal predictor. The second prediction sample and an above-row reference sample in the same column as the second prediction sample are interpolated to generate a vertical predictor. The vertical predictor and the horizontal predictor are linearly combined to generate an angular-planar prediction sample. In another method, a first predictor is generated using angular prediction and a second predictor is generated using planar prediction. The first predictor and the second predictor are linearly combined to generate a fused Intra predictor.
    Type: Application
    Filed: August 4, 2022
    Publication date: December 1, 2022
    Inventors: Chia-Ming TSAI, Han HUANG, Chih-Wei HSU, Yu-Wen HUANG
  • Patent number: 11516513
    Abstract: In one method, the current block is partitioned into multiple final sub-blocks using one or more stages of sub-tree partition comprising ternary tree partition and at least one other-type partition, where ternary partition tree is excluded from the sub-tree partition if a current sub-tree depth associated with a current sub-block is greater than a first threshold and the first threshold is an integer greater than or equal to 1. In another method, if a test condition is satisfied, the current block is encoded or decoded using a current Inter mode selected from a modified group of Inter tools, where the modified group of Inter tools is derived from an initial group of Inter tools by removing one or more first Inter tools from the initial group of Inter tools, replacing one or more second Inter tools with one or more complexity-reduced Inter tools, or both.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: November 29, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chun-Chia Chen, Chia-Ming Tsai, Yu-Chi Su, Chen-Yen Lai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang, Han Huang
  • Patent number: 11508818
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: November 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20220359516
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.
    Type: Application
    Filed: May 6, 2021
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Che-Ming HSU, Ching-Feng FU, Huan-Just LIN
  • Patent number: 11495503
    Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20220349454
    Abstract: A drive device with multiple swinging blocks drivingly connected with each other includes a driven unit connected with a driven apparatus (such as a power generation motor or a generator), a driving unit drivingly connected with the driven unit and an actuating unit connected with the driving unit. The driven unit includes a flywheel. The driving unit includes three dynamic energy modules respectively connected with the flywheel at intervals. Each dynamic energy module has a gear engaged with the flywheel and a swinging block disposed on the gear. There is a 120-degree angle difference between the corresponding angular positions of each two adjacent swinging blocks. The actuating unit includes an actuating motor, a driving member driven by the actuating motor and connected with one of the dynamic energy modules and transmission members drivingly connected with the dynamic energy modules for driving the driven unit to together rotate.
    Type: Application
    Filed: March 31, 2022
    Publication date: November 3, 2022
    Inventors: PO-CHI HSU, YU-LIEN CHU HSU, CHIA MING HSU
  • Publication number: 20220350235
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 3, 2022
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen