Patents by Inventor Yu Pei

Yu Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137110
    Abstract: A method for reducing frequency interference, and a communication satellite system. The method includes configuring the communication satellite system, determining a first range of areas in which a spatial isolation angle between the LEO satellite and the GEO satellite does not satisfy a minimum spatial isolation angle within service areas of the movable spot beams, enabling the movable spot beams to not enter the areas, and when the movable spot beams of the transmitting and receiving user antennas of multiple adjacent LEO satellites provide services to a same area, calculating a spatial isolation angles between the movable spot beams of the transmitting and receiving user antennas of any two adjacent LEO satellites, and in response to the spatial isolation angle not satisfying the minimum spatial isolation angle, assigning different sub-frequencies to the movable spot beams that do not satisfy the minimum spatial isolation angle.
    Type: Application
    Filed: September 29, 2021
    Publication date: April 25, 2024
    Inventors: Fenglong Hou, Feng Li, Xiaoxiong Lin, Yu Qi, Shengwei Pei, Dong Chen, Jie Xing, Hua Huang, Xingang Li, Jincheng Tong, Hengchao Sun, Shaoran Liu, Zeyu Bao
  • Patent number: 11966322
    Abstract: A method, computer program product and system are provided for preloading debug information based on the presence of incremental source code files. Based on parsed input parameters to a source code debugger, a source code repository and a local storage area are searched for an incremental file. In response to the incremental file being located, a preload indicator in the incremental file, which is a source code file, is set. Based on the preload indicator being set, debug symbol data from the incremental file is merged to a preload symbol list. In response to receiving a command to examine the debug symbol data from the incremental file, the preload symbol list is searched for the requested debug symbol data.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: April 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Xiao Ling Chen, Xiao Xuan Fu, Jiang Yi Liu, Zhan Peng Huo, Wen Ji Huang, Qing Yu Pei, Min Cheng, Yan Huang
  • Publication number: 20240108230
    Abstract: The embodiments of the disclosure provide a method for evaluating a health condition indicator of a subject, a host, and a computer readable storage medium. The method includes: obtaining a reference heart rate of the subject and determining a heart rate indicator of the subject according to the reference heart rate; determining a fitness indicator of the subject based on physiological information of the subject; determining an age indicator of the subject based on an age of the subject; and determining the health condition indicator of the subject at least based on the heart rate indicator, the fitness indicator, and the age indicator.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: BOMDIC INC.
    Inventors: Yao Shiao, Shao Wen Tou, Yu-Ting Liu, Amy Pei-Ling Chiu
  • Publication number: 20240105642
    Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
  • Patent number: 11942464
    Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240086358
    Abstract: A processing element array includes N processing elements (PE) arranged linearly, N?2, and an operating method of the PE array includes: performing a first data transmission procedure, where an initial value of I is 1 and the first data transmission procedure includes: operating, by an ith PE, according to a first datum stored in itself, and sending the first datum to other PEs for their operations, adding 1 to I when I<N, and performing the first data transmission procedure again, performing a second data transmission procedure when I is equal to N, which includes: operating, by the Jth PE, according to a second datum stored in itself, and sending the second datum to other PEs for their operations, reducing J by 1 when J>1 and the (J?1)th PE has the second datum, and performing the second data transmission procedure again.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 14, 2024
    Inventors: Yu-Sheng Lin, Trista Pei-Chun CHEN, Wei-Chao CHEN
  • Publication number: 20240088062
    Abstract: A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
  • Patent number: 11769652
    Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jr-Sheng Chen, An-Chi Li, Shih-Che Huang, Chih-Hsien Hsu, Zhi-Hao Huang, Ming Chih Wang, Yu-Pei Chiang, Chun Yan Chen
  • Publication number: 20230288150
    Abstract: A condensing device includes two end caps each having two openings, a barrel connected to and disposed between the end caps, a heat exchanger disposed in the barrel, and a condensing unit mounted to one end cap. The heat exchanger includes a passage and a vortex chamber each cooperating with a respective one of the openings of each of the end caps to define a flow channel to permit fluid to flow therethrough. A cooling chip module of the condensing unit includes a heat absorbing plate disposed at an end proximate to the one end cap, and a heat dissipating plate disposed at an opposite end.
    Type: Application
    Filed: August 11, 2022
    Publication date: September 14, 2023
    Applicant: EVERINN INTERNATIONAL CO., LTD.
    Inventor: Yu-Pei HO
  • Publication number: 20230288151
    Abstract: A heat exchange device includes two end caps each having two openings, a barrel connected to and disposed between the end caps, a heat exchanger disposed in the barrel, a condensing unit and an electric unit mounted respectively to the end caps. The heat exchanger includes two conduit members spaced apart by a gap, a passage unit and a vortex chamber. The condensing unit absorbing and dissipating heat of the fluid. The electric unit is co-movable with at least a portion of one of the conduit members such that a dimension of the gap is adjusted, so as to change the temperature of the fluid flowing out of the device.
    Type: Application
    Filed: August 11, 2022
    Publication date: September 14, 2023
    Applicant: EVERINN INTERNATIONAL CO., LTD.
    Inventor: Yu-Pei HO
  • Publication number: 20230280309
    Abstract: Methods and apparatus for electrochemical analysis of water include acid cleaning a quartz crystal microbalance (QCM), stabilizing a QCM in analyte solution, and analyzing the solution by chronoamperometry and measuring a frequency shift of the QCM. The method may further include cleaning the QCM in an acid solution prior to stabilizing the QCM in analyte solution. The apparatus may provide at least semi-automated electrochemical analysis of water including determining a concentration of an analyte in a water sample, and communicating the concentration of the analyte over a network. The analyte may be manganese.
    Type: Application
    Filed: February 28, 2023
    Publication date: September 7, 2023
    Inventors: Yu Pei, Zhe She, Sarah Jane Odessa Payne
  • Publication number: 20230264945
    Abstract: A micro-electromechanical-system (MEMS) device may be formed to include an anti-stiction polysilicon layer on one or more moveable MEMS structures of a device wafer of the MEMS device to reduce, minimize, and/or eliminate stiction between the moveable MEMS structures and other components or structures of the MEMS device. The anti-stiction polysilicon layer may be formed such that a surface roughness of the anti-stiction polysilicon layer is greater than the surface roughness of a bonding polysilicon layer on the surfaces of the device wafer that are to be bonded to a circuitry wafer of the MEMS device. The higher surface roughness of the anti-stiction polysilicon layer may reduce the surface area of the bottom of the moveable MEMS structures, which may reduce the likelihood that the one or more moveable MEMS structures will become stuck to the other components or structures.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: Hsi-Cheng HSU, Kuo-Hao LEE, Jui-Chun WENG, Ching-Hsiang HU, Ji-Hong CHIANG, Lavanya SANAGAVARAPU, Chia-Yu LIN, Chia-Chun HUNG, Jia-Syuan LI, Yu-Pei CHIANG
  • Patent number: 11655138
    Abstract: A micro-electromechanical-system (MEMS) device may be formed to include an anti-stiction polysilicon layer on one or more moveable MEMS structures of a device wafer of the MEMS device to reduce, minimize, and/or eliminate stiction between the moveable MEMS structures and other components or structures of the MEMS device. The anti-stiction polysilicon layer may be formed such that a surface roughness of the anti-stiction polysilicon layer is greater than the surface roughness of a bonding polysilicon layer on the surfaces of the device wafer that are to be bonded to a circuitry wafer of the MEMS device. The higher surface roughness of the anti-stiction polysilicon layer may reduce the surface area of the bottom of the moveable MEMS structures, which may reduce the likelihood that the one or more moveable MEMS structures will become stuck to the other components or structures.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Cheng Hsu, Kuo-Hao Lee, Jui-Chun Weng, Ching-Hsiang Hu, Ji-Hong Chiang, Lavanya Sanagavarapu, Chia-Yu Lin, Chia-Chun Hung, Jia-Syuan Li, Yu-Pei Chiang
  • Patent number: 11615946
    Abstract: Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jr-Sheng Chen, An-Chi Li, Shih-Che Huang, Chih-Hsien Hsu, Zhi-Hao Huang, Alex Wang, Yu-Pei Chiang, Chun Yan Chen
  • Publication number: 20220359165
    Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Jr-Sheng CHEN, An-Chi LI, Shi-Che HUANG, Chih-Hsien HSU, Zhi-Hao HUANG, Ming Chih WANG, Yu-Pei CHIANG, Chun Yan CHEN
  • Publication number: 20220359168
    Abstract: Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Jr-Sheng CHEN, An-Chi LI, Shih-Che HUANG, Chih-Hsien HSU, Zhi-Hao HUANG, Alex WANG, Yu-Pei CHIANG, Chun Yan Chen
  • Publication number: 20220338309
    Abstract: A transparent film heater is provided, including a transparent conductive film, at least two main electrodes and at least four multiple electrodes. The transparent conductive film is disposed on a transparent substrate. At least two main electrodes are arranged on two sides of the transparent conductive film along an edge of the transparent conductive film. The at least four multiple electrodes are composed of a first pair of multiple electrodes and a second pair of multiple electrodes, and are arranged on the transparent conductive film. A first spacing region and a second spacing region are respectively located between adjacent end points of the two main electrodes along the edge of the transparent conductive film. The first pair of multiple electrodes are arranged in the first spacing region, and the second pair of multiple electrodes are arranged in the second spacing region.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 20, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Li-Wei Yao, Min-Hsiung Liang, Hsiao-Fen Wei, Yu-Pei Chang, Te-Hsun Lin, Chih-Chia Chang, Yen-Shu Lee
  • Patent number: 11443825
    Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: September 13, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Yu-Feng Ho, Kuo-Min Liao, Yu-Pei Lin
  • Patent number: 11368459
    Abstract: Methods, computer program products, and/or systems are provided that can perform the following operations: receiving a connection request from a first user device; creating an authentication container for the first user device; authenticating the first user device using the authentication container; in response to authentication for the first user device being successful, creating a first user request processing container for the first user device; and processing user requests received from the first user device using the first user request processing container.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 21, 2022
    Assignee: International Business Machines Corporation
    Inventors: Heng Wang, Xiao Ling Chen, Chen Guang Liu, Wen Qi WQ Ye, Fei Tan, Lu Lu, Jing Li, Qing Yu Pei
  • Publication number: 20220172796
    Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 2, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Yu-Feng Ho, Kuo-Min Liao, Yu-Pei Lin