Patents by Inventor Yu Pei

Yu Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220338309
    Abstract: A transparent film heater is provided, including a transparent conductive film, at least two main electrodes and at least four multiple electrodes. The transparent conductive film is disposed on a transparent substrate. At least two main electrodes are arranged on two sides of the transparent conductive film along an edge of the transparent conductive film. The at least four multiple electrodes are composed of a first pair of multiple electrodes and a second pair of multiple electrodes, and are arranged on the transparent conductive film. A first spacing region and a second spacing region are respectively located between adjacent end points of the two main electrodes along the edge of the transparent conductive film. The first pair of multiple electrodes are arranged in the first spacing region, and the second pair of multiple electrodes are arranged in the second spacing region.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 20, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Li-Wei Yao, Min-Hsiung Liang, Hsiao-Fen Wei, Yu-Pei Chang, Te-Hsun Lin, Chih-Chia Chang, Yen-Shu Lee
  • Patent number: 11443825
    Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: September 13, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Yu-Feng Ho, Kuo-Min Liao, Yu-Pei Lin
  • Patent number: 11368459
    Abstract: Methods, computer program products, and/or systems are provided that can perform the following operations: receiving a connection request from a first user device; creating an authentication container for the first user device; authenticating the first user device using the authentication container; in response to authentication for the first user device being successful, creating a first user request processing container for the first user device; and processing user requests received from the first user device using the first user request processing container.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 21, 2022
    Assignee: International Business Machines Corporation
    Inventors: Heng Wang, Xiao Ling Chen, Chen Guang Liu, Wen Qi WQ Ye, Fei Tan, Lu Lu, Jing Li, Qing Yu Pei
  • Publication number: 20220172796
    Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 2, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Yu-Feng Ho, Kuo-Min Liao, Yu-Pei Lin
  • Publication number: 20220164276
    Abstract: A method, computer program product and system are provided for preloading debug information based on the presence of incremental source code files. Based on parsed input parameters to a source code debugger, a source code repository and a local storage area are searched for an incremental file. In response to the incremental file being located, a preload indicator in the incremental file, which is a source code file, is set. Based on the preload indicator being set, debug symbol data from the incremental file is merged to a preload symbol list. In response to receiving a command to examine the debug symbol data from the incremental file, the preload symbol list is searched for the requested debug symbol data.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Inventors: Xiao Ling Chen, Xiao Xuan Fu, Jiang Yi Liu, Zhan Peng Huo, Wen Ji Huang, Qing Yu Pei, Min Cheng, Yan Huang
  • Patent number: 11341121
    Abstract: An example operation may include one or more of connecting, by a service discovery node, to a blockchain configured to store workloads and stakes of a plurality of endorser nodes, receiving, by the service discovery node, a discovery query that contains an endorsement policy from a user node, generating, by the service discovery node, cryptographic sortition parameters based on the endorsement policy, sending, by the service discovery node, the cryptographic sortition parameters to the plurality of the endorser nodes, collecting, by the service discovery node, sortition labels from the plurality of the endorser nodes, the sortition labels generated based on the sortition parameters, determining, based on the sortition labels, a set of the endorser nodes from the plurality of the endorser nodes that qualify the endorsement policy, and providing, by the service discovery node, identifiers of the set of the endorser nodes to the user node for an endorsement of a user transaction proposal.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 24, 2022
    Assignee: International Business Machines Corporation
    Inventors: Zhi Guo Deng, Qi Li, Huan Wu, Shun Xian Wu, Xiao Ling Chen, Qing Yu Pei
  • Publication number: 20220135397
    Abstract: A micro-electromechanical-system (MEMS) device may be formed to include an anti-stiction polysilicon layer on one or more moveable MEMS structures of a device wafer of the MEMS device to reduce, minimize, and/or eliminate stiction between the moveable MEMS structures and other components or structures of the MEMS device. The anti-stiction polysilicon layer may be formed such that a surface roughness of the anti-stiction polysilicon layer is greater than the surface roughness of a bonding polysilicon layer on the surfaces of the device wafer that are to be bonded to a circuitry wafer of the MEMS device. The higher surface roughness of the anti-stiction polysilicon layer may reduce the surface area of the bottom of the moveable MEMS structures, which may reduce the likelihood that the one or more moveable MEMS structures will become stuck to the other components or structures.
    Type: Application
    Filed: May 4, 2021
    Publication date: May 5, 2022
    Inventors: Hsi-Cheng HSU, Kuo-Hao LEE, Jui-Chun WENG, Ching-Hsiang HU, Ji-Hong CHIANG, Lavanya SANAGAVARAPU, Chia-Yu LIN, Chia-Chun HUNG, Jia-Syuan LI, Yu-Pei CHIANG
  • Publication number: 20220103550
    Abstract: Methods, computer program products, and/or systems are provided that can perform the following operations: receiving a connection request from a first user device; creating an authentication container for the first user device; authenticating the first user device using the authentication container; in response to authentication for the first user device being successful, creating a first user request processing container for the first user device; and processing user requests received from the first user device using the first user request processing container.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Heng Wang, Xiao Ling Chen, Chen Guang Liu, Wen Qi WQ Ye, Fei Tan, Lu Lu, Jing Li, Qing Yu Pei
  • Publication number: 20220073878
    Abstract: The present invention provides a human CD16+ natural killer cell line. This human CD16+ natural killer cell line does not include synthetic, genetically modified or deliberately delivered polynucleotide encoding the CD16 receptor and is a non-tumorigenic cell line. Therefore, this human CD16+ natural killer cell line might provide considerable long-term safety for disease treatment.
    Type: Application
    Filed: January 16, 2020
    Publication date: March 10, 2022
    Applicant: Acepodia Biotechnologies Ltd.
    Inventors: Zih-Fei Cheng, Chia-Yun Lee, Hao-Kang Li, Yan-Liang Lin, Ching-Wen Hsiao, Yan-Da Lai, Yu-Pei Cheng, Hsiu-Ping Yang, Shih-Chia Hsiao
  • Publication number: 20210198684
    Abstract: A method for increasing the yield of microalgae and the yield of a product produced by the microalgae is provided. The method includes performing a change procedure on CAM1 gene and/or calmodulin 1 encoded by the CAM1 gene in a microalga, such that a change occurs in a nucleotide and/or the nucleotide sequence of the CAM1 gene and/or an amino acid and/or the amino acid sequence of the calmodulin 1 encoded by the CAM1 gene in the microalga to obtain an altered microalga. The altered microalga has an altered CAM1 gene and/or an altered calmodulin 1. The altered microalga has a higher growth rate and a higher product production rate and/or yield than an unaltered microalga.
    Type: Application
    Filed: December 28, 2020
    Publication date: July 1, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Chang-Chieh CHEN, Shao-I WU, Jo-Di CHIANG, Yu-Pei LIN, Wen-Chang LU
  • Patent number: 10964547
    Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Han Meng, Chih-Hsien Hsu, Jr-Sheng Chen, An-Chi Li, Lin-Ching Huang, Yu-Pei Chiang
  • Patent number: 10957516
    Abstract: A multi-zone gas distribution plate (GDP) for high uniformity in plasma-based etching is provided. A housing defines a process chamber and comprises a gas inlet configured to receive a process gas. A GDP is arranged in the process chamber and is configured to distribute the process gas within the process chamber. The GDP comprises a plurality of holes extending through the GDP, and further comprises a plurality of zones into which the holes are grouped. The zones comprise a first zone and a second zone. Holes of the first zone share a first cross-sectional profile and holes of the second zone share a second cross-sectional profile different than the first cross-sectional profile. A method for designing the multi-zone GDP is also provided.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Han Meng, Jr-Sheng Chen, Yin-Tun Chou, Chih-Hua Chan, Lin-Ching Huang, Yu-Pei Chiang
  • Publication number: 20200233858
    Abstract: An example operation may include one or more of connecting, by a service discovery node, to a blockchain configured to store workloads and stakes of a plurality of endorser nodes, receiving, by the service discovery node, a discovery query that contains an endorsement policy from a user node, generating, by the service discovery node, cryptographic sortition parameters based on the endorsement policy, sending, by the service discovery node, the cryptographic sortition parameters to the plurality of the endorser nodes, collecting, by the service discovery node, sortition labels from the plurality of the endorser nodes, the sortition labels generated based on the sortition parameters, determining, based on the sortition labels, a set of the endorser nodes from the plurality of the endorser nodes that qualify the endorsement policy, and providing, by the service discovery node, identifiers of the set of the endorser nodes to the user node for an endorsement of a user transaction proposal.
    Type: Application
    Filed: January 22, 2019
    Publication date: July 23, 2020
    Inventors: Zhi Guo Deng, Qi Li, Huan Wu, Shun Xian Wu, Xiao Ling Chen, Qing Yu Pei
  • Patent number: 10654713
    Abstract: Methods for manufacturing MEMS structures are provided. The method for manufacturing a microelectromechanical system (MEMS) structure includes etching a MEMS substrate to form a first trench and a second trench and etching the MEMS substrate through the first trench and the second trench to form a first through hole and an extended second trench. The method for manufacturing a MEMS structure further includes etching the MEMS substrate through the extended second trench to form a second through hole. In addition, a height of the first trench is greater than ¾ of a height of the MEMS substrate, and a height of the second trench is smaller than ? of the height of the MEMS substrate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Han Meng, Jr-Sheng Chen, Chih-Hsien Hsu, Yu-Pei Chiang, Lin-Ching Huang
  • Publication number: 20200098583
    Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Han Meng, Chih-Hsien Hsu, Jr-Sheng Chen, An-Chi Li, Lin-Ching Huang, Yu-Pei Chiang
  • Publication number: 20200075294
    Abstract: Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.
    Type: Application
    Filed: May 24, 2019
    Publication date: March 5, 2020
    Inventors: Jr-Sheng CHEN, An-Chi Li, Shih-Che Huang, Chih-Hsien Hsu, Zhi-Hao Huang, Alex Wang, Yu-Pei Chiang, Chen-Chun Yan
  • Publication number: 20200043705
    Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 6, 2020
    Inventors: Jr-Sheng CHEN, An-Chi Li, Shih-Che Huang, Chih-Hsien Hsu, Zhi-Hao Huang, Alex Wang, Yu-Pei Chiang, Chen-Chun Yan
  • Patent number: 10529578
    Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Han Meng, Chih-Hsien Hsu, Jr-Sheng Chen, An-Chi Li, Lin-Ching Huang, Yu-Pei Chiang
  • Publication number: 20190358653
    Abstract: A cyclone filtering device includes first and second filters. The first filter includes a first filtering tube defining a first turbulence room, and has a coupling cover communicated with the first turbulence room and disposed for allowing passage of fluid, and a barrel seat defining a dust collecting room that is communicated with the first turbulence room. The second filter includes a second filtering tube defining a second turbulence room that is communicated with the first turbulence room, two end covers having an end opening that is communicated with the second turbulence room, and a capture member disposed in the second turbulence room and disposed for capturing substances that are entrained in the fluid.
    Type: Application
    Filed: May 23, 2018
    Publication date: November 28, 2019
    Inventor: Yu-Pei Ho
  • Publication number: 20190256350
    Abstract: Methods for manufacturing MEMS structures are provided. The method for manufacturing a microelectromechanical system (MEMS) structure includes etching a MEMS substrate to form a first trench and a second trench and etching the MEMS substrate through the first trench and the second trench to form a first through hole and an extended second trench. The method for manufacturing a MEMS structure further includes etching the MEMS substrate through the extended second trench to form a second through hole. In addition, a height of the first trench is greater than ¾ of a height of the MEMS substrate, and a height of the second trench is smaller than ? of the height of the MEMS substrate.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 22, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Han MENG, Jr-Sheng CHEN, Chih-Hsien HSU, Yu-Pei CHIANG, Lin-Ching HUANG