Abstract: An all-in-one computer includes a monitor and a host. The monitor includes a display screen, which has an accommodating cavity with an opening located on a peripheral side of the display screen, and the host is detachably mounted in the accommodating cavity from the opening along a first direction. The monitor is provided with a first connecting assembly, the host is provided with a second connecting assembly, and when the host is mounted in the accommodating cavity, the second connecting assembly is connected to the first connecting assembly to implement signal transmission between the host and the monitor. An arrangement direction of the second connecting assembly and the first connecting assembly is perpendicular to the first direction, and the arrangement direction of the second connecting assembly and the first connecting assembly is parallel to a plane on which the display screen is located.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: This application provides a service process invoking method and a related apparatus. The method includes: An application process obtains a context of a binder process; the application process obtains a handle of a service process based on the context of the binder process; the application process runs a program of the binder process based on the context of the binder process, to obtain a context of the service process based on the handle of the service process; and the application process runs a program of the service process based on the context of the service process, to respond to a binder request of the application process, where the binder request is used to request a system service provided by the service process. In embodiments of this application, actual power consumption is accurately reflected.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: A method for detecting defects on a wafer including the steps of obtaining a reference image of a chip pattern formed on a reference wafer, using a computer algorithm to analyze the reference image to produce a division map for the chip pattern; setting respective thresholds for divisions of the division map, obtaining a comparison data between a test image of the chip pattern formed on a test wafer and the reference image, using the division map and the thresholds to examine the comparison data to identify a defect in the test image.

Abstract: An apparatus includes a laminate, the laminate including a dielectric layer having a first surface and a second surface opposed to the first surface, and a conductive layer forming a circuit element overlying the first surface of the dielectric layer. The apparatus further includes a magnetic layer over the conductive layer. A first edge surface of the magnetic layer is coplanar with a first edge surface of the laminate, and a second edge surface of the magnetic layer is coplanar with a second edge surface of the laminate.

Abstract: A display device includes first and second display modules and first and second turning pieces that include a first coupling piece, a first turning piece, a second turning piece, and a third turning piece, a second coupling piece and a guiding device. When the first and second display modules are switched between folding and unfolding, the first turning piece pivots relative to the first coupling piece and the second turning piece, and the third turning piece pivots relative to the second coupling piece and the second turning piece. When the display module is switched from folded to unfolded, the other side of the first display module relative to the side is pulled, the side of the first display module is guided by one end of the guiding device and slides to the other end, the first and second display modules are symmetrically unfolded with the side edge as the center.

Abstract: The present invention discloses a vessel tracking and monitoring system and operating method thereof. Specifically, the vessel tracking and monitoring system comprises at least one camera, a processing module and a storage module. On the other hand, the processing module may keep the water object which is detected and recognized by the at least one camera in the center area of a monitoring screen. Therefore, the present invention may track and recognize the type of the at least one water object, assisting areas such as ports in managing and tracking water object arrivals and departures under various environmental conditions.

Abstract: The present disclosure provides a gene combination for expressing and producing terrequinone A in Escherichia coli and use thereof. The gene combination includes a tdiAS gene, a tdiBS gene, a tdiCS gene, a tdiDS gene, a tdiES gene, an sfpS gene, an ScCKS gene, and an AtIPKS gene with nucleotide sequences set forth in SEQ ID NOS:1 to 8. In the present disclosure, a recombinant engineered strain capable of producing terrequinone A having anti-cancer activity is obtained by separately constructing recombinant plasmids pC02 and pU03 through the eight genes and transforming the two recombinant plasmids into E. coli. The content of terrequinone A in a fermentation broth thereof is 106.3 mg/L, which has potential application value in the biopharmaceutical field.

Abstract: A series-parallel monorail hoist based on an oil-electric hybrid power and a controlling method thereof. The monorail hoist includes a cabin, a hydraulic driving system, a lifting beam, a gear track driving and energy storage system, and a speed adaptive control system connected in series with each other and travelling on a track. The monorail hoist is capable of implementing an independent drive by an electric motor or a diesel engine in an endurance mode, a hybrid drive of the electric motor and the diesel engine in a transportation mode, and a hybrid drive of the diesel engine and a flywheel energy storage system in a climbing mode, according to different operating conditions that include conditions of an upslope, a downslope and a load. Power requirements for the monorail hoist under various operating conditions are satisfied, and the excess energy is recovered during the process of travelling.

Abstract: A packet forwarding method and apparatus, and a communication network, related to the field of communication technologies. In the solutions provided, a controller may obtain a correspondence between an application-aware identifier of a service flow and a network service required for transmitting the service flow, and deliver the correspondence to a network device. Further, when identifying the service flow as a service flow indicated by the application-aware identifier, the network device may directly forward a packet of the service flow by using the corresponding network service. The controller may establish and deliver the correspondence between the application-aware identifier and the network service, so that the network device can directly forward the service packet of the service flow based on the correspondence. Therefore, flexibility of forwarding the service packet is effectively improved.

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a MIM structure, a first contact and a second contact. The MIM structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, and a top electrode layer on the ferroelectric layer. The ferroelectric layer is substantially made of lead zirconate titanate (PZT), BaTiO3 (BTO), or barium strontium titanate (BST), and a thickness of the ferroelectric layer is greater than a thickness of the dielectric layer.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: A connecting structure includes a first dielectric layer, a first connecting via in the first dielectric layer, a second connecting via in the first dielectric layer, and an isolation between the first connecting via and the second connecting via. The isolation separates the first and second connecting vias from each other. The first connecting via, the isolation and the second connecting via are line symmetrical about a central line perpendicular to a top surface of the first dielectric layer.

Abstract: The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion.