Abstract: An apparatus for mode detection for a display device includes a front-end circuit, adapted to fetch an image signal according to a determined mode to generate a fetched image signal, and to adjust the determined mode according to a control signal, and a back-end circuit, connected to the front-end circuit, adapted to process the fetched image signal according to the determined mode. The back-end circuit is adapted to generate an indication signal according to an abnormal status, wherein the back-end circuit comprises a buffer adapted to temporarily store the fetched image signal, and wherein the abnormal status comprises an underflow or overflow state of the buffer. The back-end circuit further includes a determining unit, connected to the front-end circuit and the back-end circuit, adapted to generate the control signal according to the indication signal indicating the determined mode needs to adjust.

Abstract: An apparatus for mode detection for a display device includes a front-end circuit, adapted to fetch an image signal according to a determined mode to generate a fetched image signal, and to adjust the determined mode according to a control signal, and a back-end circuit, connected to the front-end circuit, adapted to process the fetched image signal according to the determined mode. The back-end circuit is adapted to generate an indication signal according to an abnormal status, wherein the back-end circuit comprises a buffer adapted to temporarily store the fetched image signal, and wherein the abnormal status comprises an underflow or overflow state of the buffer. The back-end circuit further includes a determining unit, connected to the front-end circuit and the back-end circuit, adapted to generate the control signal according to the indication signal indicating the determined mode needs to adjust.

Abstract: The invention discloses a mode detection circuit and a method thereof, for detecting an image signal, the image signal includes a horizontal resolution and the vertical resolution. The mode detection circuit includes a measuring unit, a calculation unit, and a decision unit. The measuring unit receives a clock signal and is used to count the clock signal to output a first counting value and the second counting value. The calculation unit is used to perform the calculation with the first counting value and the second counting value and thereby outputting a calculating value, wherein the calculating value outputted by the calculation unit is corresponding to the ratio of the first counting value to the second counting value. The decision unit is used to determine the horizontal resolution or the vertical resolution according to the calculating value.

Abstract: A timing controller for a display processing device includes: a plurality of predetermined pins for receiving an image signal by a pin-share method, wherein the image signal is a first format image signal or a second format image signal; a detector coupled to the predetermined pins and for detecting at least one of the predetermined pins to determine whether the image signal is the first format image signal or the second format image signal and outputting a detection result; and a processor coupled to the detector and for processing the image signal according to the detection result to generate and output a timing control signal.

Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

Abstract: A method for controlling a display device is disclosed. The method includes receiving an input video image having a plurality of active scan lines, controlling the display device to display a plurality of background scan lines on a first display area with a first scan line frequency, and controlling the display device to display an output image on a second display area with a second scan line frequency. A second aspect ratio of the output image is substantially equal to a first aspect ratio of the input video image. The second scan line frequency is substantially lower than the first scan line frequency.

Abstract: A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

Abstract: A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.

Abstract: The invention discloses a display control device and method thereof. The display control device and method thereof utilize the phase deviation and the frequency deviation between the output signal and the input signal caused during channel switching to provide converting time acceptable by a display device and to achieve the objective of balancing the data stream transmission.

Abstract: A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.

Abstract: A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.

Abstract: The present invention discloses a signal receiving method for determining a transmission format of an input signal and a related signal receiving circuit. The signal receiving method includes: receiving the input signal; generating a signal detecting result corresponding to at least a signal transmission channel of a plurality of signal transmission channels according to an output result of the signal transmission channel; and determining the transmission format of the input signal according to the signal detecting result. The signal receiving circuit includes: an input interface, for receiving an input signal; a detecting module, for generating a signal detecting result corresponding to at least a signal transmission channel of a plurality of signal transmission channels according to an output result of the signal transmission channel; and a determining unit, for determining the transmission format of the input signal according to the signal detecting result.

Abstract: The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.

Abstract: A noise processing device and its method are provided for a video/audio system having a high definition multimedia interface (HDMI). The noise processing device includes a detecting unit, a signal generating unit, and a decision unit. The noise processing method includes using the detecting unit to monitor a variation related to an audio signal and generate a detecting signal accordingly; using the signal generating unit to produce an adjustment signal according to the detecting signal; and using the decision unit to produce an output audio signal according to the audio signal and the adjustment signal. Another embodiment of the noise processing device includes a compensation tracking unit having a control unit. The compensation tracking unit produces an output audio signal according to a difference between the output audio signal itself and the audio signal and a gain of the control unit.

Abstract: The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.

Abstract: A method to assess signal transmission quality and the adjust method thereof are proposed. First, different time points of a control signal at a receiving end are acquired and the number of signal transitions in a predetermined time interval is counted. Next, the number of signal transitions is recorded and compared to a reference value to obtain a comparison result. The quality of the control signal is then determined based on the comparison result. The parameter setting of the receiving end is adjusted according to the quality of the control signal received by the receiving end to get a better performance setting.

Abstract: A method for generating a video clock and an associated target image frame is disclosed. The method generates an output clock signal for outputting a target image frame to a panel according to a frame pixel number and a vertical synchronization signal (Vsync). The target image frame corresponds to a source image frame. The frame pixel number is the number of total pixels included in a predetermined frame format, and the Vsync signal is an input Vsync signal or an output Vsync signal. The period of the output clock signal is the result of the period of the Vsync divided by the frame pixel number. In this manner, the format of the target image frame can remain substantially fixed, and is substantially equal to the predetermined frame format.

Abstract: A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

Abstract: A frame synchronization method includes: temporarily storing input data of at least one source frame in a frame buffer according to an input time sequence; generating an output time sequence according to the input time sequence and a delay time; generating output data of a destination frame according to the input data of the source frame; and outputting the output data of the destination frame according to an output time sequence; wherein an average frame rate of the source frame is substantially the same as that of the destination frame.

Abstract: A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.