Abstract: An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.

Abstract: A data transfer interface apparatus and method for controlling data transfer. The data transfer interface apparatus includes a first storage unit for storing an input data according to a first clock and for outputting a first output data according to a second clock, a single-port memory coupled to the first storage unit for storing the first output data according to the second clock and for outputting a second output data according to the second clock, and a second storage unit coupled to the single-port memory for storing the second output data according to the second clock and for outputting a third output data according to a third clock.

Abstract: The present invention discloses an apparatus for evaluating a transmission quality of data display system and its related method. The method comprises: mixing at least one pattern in a first signal of an image signal to produce a mixed signal in the transmitter, wherein said pattern is known to said receiver; transferring the mixed signal to the receiver through a channel; separating the received mixed signal into a received signal and a received pattern in the receiver; and evaluating the transmission quality of the display system according to the pattern and the received pattern.

Abstract: A method for dithering an image is disclosed, which includes: storing a plurality of dithering parameters corresponding to a predetermined function for a predetermined input intensity range; and dithering pixels of the predetermined input intensity range according to the plurality of dithering parameters.

Abstract: A method for up/down converting display data employs steps of generating a first clock signal, generating display data, writing the display data into a buffer using the first clock signal, generating a second clock signal, reading out the display data written into the buffer using the second signal, and transmitting the read-out display data to a display module.

Abstract: A method to assess signal transmission quality and the adjust method thereof are proposed. First, different time points of a control signal at a receiving end are acquired and the number of signal transition in a predetermined time interval is counted. Next, the number of signal transition is recorded and compared to obtain a comparison result. The quality of control signal is then determined based on the comparison result. Besides, the parameter setting of the receiving end is adjusted according to the quality of the control signal received by the receiving end to get a better performance setting.

Abstract: A method for adjusting a phase of a sampling frequency of ADC is disclosed. The method includes converting an analog signal into a first digital signal according to a first phase of the sampling frequency during a first time interval; calculating a first value according to the first digital signal; converting the analog signal into a second digital signal according to a second phase of the sampling frequency during a second time interval; calculating a second value according to the second digital signal; and adjusting the phase of the sampling frequency according to the first value and the second value.

Abstract: An apparatus for channel balancing of a multi-channel analog-to-digital converter of a digital image display comprises a red, a green and a blue analog-to-digital converter for respectively receiving a red, a green and a blue analog signal of an image signal wherein the analog-to-digital converters respectively sample the red, green and blue analog signals through a sampling clock signal and output a corresponding digital signal. A phase difference processing unit is used for estimating the phase differences among the digital signals and outputting corresponding time delay signals according to the phase differences. A clock delay compensation unit is used for receiving the time delay signals and respectively compensating the time delays of the sampling clock signals of the analog-to-digital converters according to the time delay signals, thereby decreasing the phase differences among the digital signals.

Abstract: A phase-locked loop includes a phase/frequency detector for generating phase error signal according to a reference signal and an input signal, a charge pump for outputting a voltage signal according to the phase error signal, a voltage-controlled oscillator for outputting an output signal corresponding to the phase error signal according to the voltage signal, an adaptive adjusting unit for outputting a control signal according to the phase error signal, so as to form a nonlinear between the output signal and the phase error signal.

Abstract: A method for adjusting parameters of an adaptive equalizer makes use of a transmitted signal received by a receiving end to adjust parameters of an adaptive equalizer. First, signal strengths of a first frequency band and a second frequency band in the transmitted signal are detected. The signal strengths of the first frequency band and the second frequency band are then compared to get a compensation ratio, i.e., the total compensation quantity of the first frequency band to the second frequency band. Finally, the parameter setting of the equalizer is adjusted according to feedback of the compensation ratio. Optimum gain control of the adaptive equalizer can thus be accomplished to compensate signal attenuation to the transmitted signal caused by the channel.

Abstract: A method for controlling an LCD to display an image. The method includes receiving a display data flow, generating a polarity signal, generating a gray-scale signal according to the polarity signal and the display data flow, and driving a pixel unit to display image according to the gray-scale signal. The polarity signal is substantially DC-balanced. A display utilizing such method may reduce the influence of flicker phenomenon.

Abstract: A digital fractional phase detector is shown that uses a phase error detector for generating a phase error signal based on the phase difference between a reference clock signal and a feedback clock signal. A quantizer directly measures the pulse width of a phase error signal and outputs the value in a digital form. By directly measuring the phase error signal, quantization accuracy is increased. In order to calibrate the digital fractional phase detector, a calibration pulse generator generates a calibration pulse of a known duration and passes it to the quantizer.

Abstract: A digital fractional phase detector is shown that uses a phase error detector for generating a phase error signal based on the phase difference between a reference clock signal and a feedback clock signal. A quantizer directly measures the pulse width of a phase error signal and outputs the value in a digital form. By directly measuring the phase error signal, quantization accuracy is increased. In order to calibrate the digital fractional phase detector, a calibration pulse generator generates a calibration pulse of a known duration and passes it to the quantizer.

Abstract: A phase frequency detector includes a phase error detector outputting a phase error signal according to a first input signal and a second input signal; a phase error judgment unit outputting a phase error judgment signal according to the first input signal and the second input signal; and a reset unit outputting a first reset signal to reset the phase error detector, and outputting a second reset signal to reset the phase error judgment unit, according to the phase error judgment signal.

Abstract: A phase frequency detector used in a phase locked loop includes a phase error detecting unit for outputting phase error signals according to a phase error between a first input signal and a second input signal, and a reset unit coupled to the phase error detecting unit. The reset unit outputs reset signals according to the first and second input signals so as to reset the phase error detecting unit without delay time. Thus, it is possible to make the output timing of the phase error signal in a more precisely linear proportion to the phase error value and to enhance the sensitivity of the phase locked loop.