Patents by Inventor Yu-Po Wang
Yu-Po Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12046823Abstract: A communication device includes a nonconductive track, an antenna element, a first turning wheel, and a second turning wheel. The antenna element is disposed on the nonconductive track. The first turning wheel and the second turning wheel drive the nonconductive track according to a control signal, so as to adjust the position of the antenna element. The communication device provides an almost omnidirectional radiation pattern.Type: GrantFiled: April 4, 2022Date of Patent: July 23, 2024Assignee: HTC CORPORATIONInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
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Publication number: 20240153884Abstract: An electronic package is provided, in which a first electronic element and a second electronic element stacked on each other are embedded in a cladding layer, a circuit structure electrically connected to the second electronic element is formed on the cladding layer, and a passive element and a package module are disposed on the circuit structure, so as to shorten the transmission distance of electrical signals between the package module and the second electronic element.Type: ApplicationFiled: December 30, 2022Publication date: May 9, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yi-Min FU, Hung-Kai WANG, Chi-Ching HO, Yih-Jenn JIANG, Yu-Po WANG
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Publication number: 20240096835Abstract: A method of manufacturing an electronic package is provided, in which an electronic element is disposed on a carrier structure; a heat dissipation body of a heat dissipation structure is disposed on the electronic element via a heat dissipation material; the heat dissipation material is cured; supporting legs of the heat dissipation structure are fixed on the carrier structure via a bonding layer; and the bonding layer is cured. Therefore, the heat dissipation structure can be effectively fixed to the heat dissipation material and the bonding layer by completing the arrangements of the heat dissipation material and the bonding layer in stages.Type: ApplicationFiled: November 16, 2022Publication date: March 21, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Pin-Jing SU, Liang-Yi HUNG, Yu-Po WANG
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Publication number: 20240038685Abstract: An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.Type: ApplicationFiled: September 22, 2022Publication date: February 1, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Fang-Lin Tsai
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Publication number: 20230378072Abstract: An electronic package is provided, in which a plurality of electronic elements are disposed on a plurality of carrier structures, and at least one bridging element is disposed between at least two of the carrier structures to electrically bridge the two carrier structures. Therefore, when there is a need to increase the function of the electronic package, only one electronic element is arranged on a single carrier structure, and there is no need to increase the panel area of the carrier structure, so as to facilitate the control of the panel area of the carrier structure and avoid warpage of the carrier structure due to the oversized panel.Type: ApplicationFiled: July 5, 2022Publication date: November 23, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Shuai-Lin Liu, Nai-Hao Kao, Chao-Chiang Pu, Yi-Min Fu, Yu-Po Wang
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Publication number: 20230282586Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.Type: ApplicationFiled: May 10, 2022Publication date: September 7, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Shuai-Lin Liu
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Publication number: 20230253331Abstract: An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.Type: ApplicationFiled: August 29, 2022Publication date: August 10, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yi-Min Fu, Chi-Ching Ho, Chao-Chiang Pu, Yu-Po Wang
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Publication number: 20230154865Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.Type: ApplicationFiled: January 10, 2022Publication date: May 18, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Po-Yuan Su
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Patent number: 11631675Abstract: A semiconductor memory structure includes a semiconductor substrate including an active region and a chop region. The semiconductor memory structure also includes an isolation structure disposed in the chop region, a first gate structure extending at least through the isolation structure in the chop region, and a second gate structure extending at least through the active region. The semiconductor memory structure also includes a doped region disposed in the active region. A first distance between the doped region and the first gate structure is shorter than a second distance between the doped region and the second gate structure.Type: GrantFiled: January 28, 2021Date of Patent: April 18, 2023Assignee: WINBOND ELECTRONICS CORP.Inventors: Yu-Po Wang, Yi-Hao Chien, Hsiang-Po Liu
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Publication number: 20230111192Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.Type: ApplicationFiled: November 16, 2021Publication date: April 13, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yi-Min Fu, Chi-Ching Ho, Cheng-Yu Kang, Yu-Po Wang
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Publication number: 20230027841Abstract: A communications apparatus includes a radio transceiver transmitting or receiving wireless signals in a wireless network and a processor coupled to the radio transceiver. The processor is configured to perform operations comprising: transmitting pre-schedule mechanism assistance information to a network device in the wireless network for the network device to refer to for uplink (UL) resource allocation regarding a pre-schedule mechanism; receiving one or more uplink (UL) grants from the network device; and performing UL transmission to the network device responsive to receiving the one or more UL grants.Type: ApplicationFiled: July 5, 2022Publication date: January 26, 2023Applicant: MEDIATEK INC.Inventors: Chiao-Chih Chang, Jianwei Zhang, Yu-Po Wang, Jun-Jie Su
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Publication number: 20220399246Abstract: An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.Type: ApplicationFiled: June 1, 2022Publication date: December 15, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yi-Min Fu, Chi-Ching Ho, Yu-Po Wang
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Publication number: 20220238526Abstract: A semiconductor memory structure includes a semiconductor substrate including an active region and a chop region. The semiconductor memory structure also includes an isolation structure disposed in the chop region, a first gate structure extending at least through the isolation structure in the chop region, and a second gate structure extending at least through the active region. The semiconductor memory structure also includes a doped region disposed in the active region. A first distance between the doped region and the first gate structure is shorter than a second distance between the doped region and the second gate structure.Type: ApplicationFiled: January 28, 2021Publication date: July 28, 2022Inventors: Yu-Po WANG, Yi-Hao CHIEN, Hsiang-Po LIU
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Publication number: 20210398985Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer.Type: ApplicationFiled: June 7, 2021Publication date: December 23, 2021Inventors: Wei-Che CHANG, Kai JEN, Yu-Po WANG
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Patent number: 9356008Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.Type: GrantFiled: February 6, 2015Date of Patent: May 31, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Hsin-Ta Lin, Fu-Tang Huang, Yu-Po Wang, Lung-Yuan Wang, Chu-Chi Hsu, Chia-Kai Shih
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Patent number: 9269677Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.Type: GrantFiled: November 3, 2014Date of Patent: February 23, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
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Publication number: 20160020195Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.Type: ApplicationFiled: February 6, 2015Publication date: January 21, 2016Inventors: Cheng-Chia Chiang, Hsin-Ta Lin, Fu-Tang Huang, Yu-Po Wang, Lung-Yuan Wang, Chu-Chi Hsu, Chia-Kai Shih
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Publication number: 20150050782Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.Type: ApplicationFiled: November 3, 2014Publication date: February 19, 2015Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
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Patent number: 8901729Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.Type: GrantFiled: June 7, 2012Date of Patent: December 2, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
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Publication number: 20130161837Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.Type: ApplicationFiled: June 7, 2012Publication date: June 27, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang