Patents by Inventor Yu Saitoh
Yu Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9793365Abstract: A trench having an opening and a corner portion is formed in a silicon carbide substrate. A corner insulating film is formed to cover the corner portion. A gate insulating film is formed to cover a region extending from the opening to the corner portion. The step of forming the gate insulating film includes a step of thermally oxidizing the trench provided with the corner insulating film. The step of thermally oxidizing the trench includes a step of heating the silicon carbide substrate at not less than 1300° C. Accordingly, sufficient insulation reliability of the gate insulating film is secured near the opening of the trench while preventing dielectric breakdown of the gate oxide film at the bottom portion of the trench.Type: GrantFiled: March 5, 2014Date of Patent: October 17, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yu Saitoh, Takeyoshi Masuda, Kenji Hiratsuka
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Publication number: 20170229305Abstract: A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.Type: ApplicationFiled: April 26, 2017Publication date: August 10, 2017Inventors: Kosuke UCHIDA, Takeyoshi MASUDA, Yu SAITOH
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Patent number: 9728633Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer having a main surface, the main surface being provided with a trench which has a bottom portion and a sidewall inclined with respect to the main surface; a gate insulating film covering each of the bottom portion and the sidewall; a gate electrode provided at least on the gate insulating film; and an upper insulating film provided on the main surface and having a part which protrudes into the trench.Type: GrantFiled: September 8, 2014Date of Patent: August 8, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Keiji Wada, Takeyoshi Masuda, Yu Saitoh
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Patent number: 9716157Abstract: A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.Type: GrantFiled: August 4, 2016Date of Patent: July 25, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Yu Saitoh
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Publication number: 20170170281Abstract: A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d0. A portion of the side wall portion on the second side surface has a minimum thickness d1. A portion, connected to the bottom portion, of the side wall portion on the first side surface has a thickness d2. Moreover, d2>d1 and d2>d0 are satisfied.Type: ApplicationFiled: February 28, 2017Publication date: June 15, 2017Inventors: Kenji Hiratsuka, Yu Saitoh, Takeyoshi Masuda
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Patent number: 9679986Abstract: A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained.Type: GrantFiled: December 2, 2015Date of Patent: June 13, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takeyoshi Masuda, Yu Saitoh, Hideki Hayashi, Toru Hiyoshi, Keiji Wada
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Patent number: 9666681Abstract: A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.Type: GrantFiled: February 4, 2014Date of Patent: May 30, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kosuke Uchida, Takeyoshi Masuda, Yu Saitoh
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Patent number: 9627487Abstract: A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d0. A portion of the side wall portion on the second side surface has a minimum thickness d1. A portion, connected to the bottom portion, of the side wall portion on the first side surface has a thickness d2. Moreover, d2>d1 and d2>d0 are satisfied.Type: GrantFiled: March 5, 2014Date of Patent: April 18, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kenji Hiratsuka, Yu Saitoh, Takeyoshi Masuda
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Publication number: 20170047415Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate oxide film, and a gate electrode. A trench is provided in the main surface to have a side surface and a bottom portion. A contact point between a first side surface portion and a second side surface portion is located in a third impurity region. An angle formed by the first side surface portion and a straight line extending through the contact point and parallel to the main surface is smaller than an angle formed by the second side surface portion and a boundary surface between a first impurity region and a second impurity region. A thickness of a portion of the gate oxide film on the contact point between the main surface and the first side surface portion is larger than a thickness of a portion of the gate oxide film on the second impurity region.Type: ApplicationFiled: April 9, 2015Publication date: February 16, 2017Inventors: Yu Saitoh, Tomoaki Hatayama, Takeyoshi Masuda
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Publication number: 20160343820Abstract: A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.Type: ApplicationFiled: August 4, 2016Publication date: November 24, 2016Inventors: Toru Hiyoshi, Yu Saitoh
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Patent number: 9490319Abstract: The trench has, in a cross-sectional view, a first corner portion which is an intersection between a first sidewall surface and a bottom portion and a second corner portion which is an intersection between a second sidewall surface and the bottom portion. A first layer has a second-conductivity-type region. In a cross-sectional view, the second-conductivity-type region is arranged to intersect with a line which passes through any of the first corner portion and the second corner portion and is in parallel to a <0001> direction of a silicon carbide crystal forming the silicon carbide layer. A ratio calculated by dividing SP by ST is not lower than 20% and not higher than 130%, where ST represents a total area of the trenches in a boundary surface between the first layer and a second layer and SP represents a total area of the second-conductivity-type regions in a plan view.Type: GrantFiled: February 4, 2014Date of Patent: November 8, 2016Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Yu Saitoh, Takeyoshi Masuda
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Publication number: 20160270690Abstract: A magnetic resonance imaging apparatus according to the invention includes a magnet device that generates a static magnetic field and a gradient magnetic field in an imaging space, a top plate that is provided to freely travel on a bed and sends an object lying thereon into the imaging space, a top plate reception member that is disposed inside the imaging space and has a traveling surface of the top plate, a top plate support column that supports the top plate reception member, and a top plate support pedestal that supports a lower end of the top plate support column, in which the top plate support pedestal is provided on a floor surface on which the magnet device is provided, via a magnet support leg, and is provided so that a movement in a direction along at least the floor surface is restricted to the magnet support leg.Type: ApplicationFiled: October 23, 2014Publication date: September 22, 2016Inventors: Yu SAITOH, Satoshi YAMASHITA
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Patent number: 9450060Abstract: A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.Type: GrantFiled: October 8, 2013Date of Patent: September 20, 2016Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Yu Saitoh
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Publication number: 20160247911Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer having a main surface, the main surface being provided with a trench which has a bottom portion and a sidewall inclined with respect to the main surface; a gate insulating film covering each of the bottom portion and the sidewall; a gate electrode provided at least on the gate insulating film; and an upper insulating film provided on the main surface and having a part which protrudes into the trench.Type: ApplicationFiled: September 8, 2014Publication date: August 25, 2016Inventors: Toru Hiyoshi, Keiji Wada, Takeyoshi Masuda, Yu Saitoh
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Publication number: 20160181372Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.Type: ApplicationFiled: June 10, 2014Publication date: June 23, 2016Inventors: Keiji Wada, Takeyoshi Masuda, Hideto Tamaso, Yu Saitoh, Toru Hiyoshi, Mitsuhiko Sakai
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Patent number: 9362121Abstract: A silicon carbide substrate including a first impurity region, a well region, and a second impurity region separated from the first impurity region by the well region is prepared. A silicon dioxide layer is formed in contact with the first impurity region and the well region. A gate electrode is formed on the silicon dioxide layer. A silicon-containing material is formed on the first impurity region. The silicon-containing material is oxidized. The silicon dioxide layer includes a first silicon dioxide region on the first impurity region and a second silicon dioxide region on the well region. The thickness of the first silicon dioxide region is greater than the thickness of the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved switching characteristics while suppressing a decrease in drain current, and a method of manufacturing the same can be provided.Type: GrantFiled: October 8, 2013Date of Patent: June 7, 2016Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Yu Saitoh
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Publication number: 20160087065Abstract: A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained.Type: ApplicationFiled: December 2, 2015Publication date: March 24, 2016Inventors: Takeyoshi Masuda, Yu Saitoh, Hideki Hayashi, Toru Hiyoshi, Keiji Wada
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Publication number: 20160064490Abstract: A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d0. A portion of the side wall portion on the second side surface has a minimum thickness d1. A portion, connected to the bottom portion, of the side wall portion on the first side surface has a thickness d2. Moreover, d2>d1 and d2>d0 are satisfied.Type: ApplicationFiled: March 5, 2014Publication date: March 3, 2016Inventors: Kenji HIRATSUKA, Yu SAITOH, Takeyoshi MASUDA
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Publication number: 20160049485Abstract: A trench having an opening and a corner portion is formed in a silicon carbide substrate. A corner insulating film is formed to cover the corner portion. A gate insulating film is formed to cover a region extending from the opening to the corner portion. The step of forming the gate insulating film includes a step of thermally oxidizing the trench provided with the corner insulating film. The step of thermally oxidizing the trench includes a step of heating the silicon carbide substrate at not less than 1300° C. Accordingly, sufficient insulation reliability of the gate insulating film is secured near the opening of the trench while preventing dielectric breakdown of the gate oxide film at the bottom portion of the trench.Type: ApplicationFiled: March 5, 2014Publication date: February 18, 2016Inventors: Yu SAITOH, Takeyoshi MASUDA, Kenji HIRATSUKA
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Publication number: 20160005826Abstract: A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.Type: ApplicationFiled: February 4, 2014Publication date: January 7, 2016Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kosuke Uchida, Takeyoshi Masuda, Yu Saitoh