Abstract: The trench has, in a cross-sectional view, a first corner portion which is an intersection between a first sidewall surface and a bottom portion and a second corner portion which is an intersection between a second sidewall surface and the bottom portion. A first layer has a second-conductivity-type region. In a cross-sectional view, the second-conductivity-type region is arranged to intersect with a line which passes through any of the first corner portion and the second corner portion and is in parallel to a <0001> direction of a silicon carbide crystal forming the silicon carbide layer. A ratio calculated by dividing SP by ST is not lower than 20% and not higher than 130%, where ST represents a total area of the trenches in a boundary surface between the first layer and a second layer and SP represents a total area of the second-conductivity-type regions in a plan view.

Abstract: A silicon carbide substrate including a first impurity region, a well region, and a second impurity region separated from the first impurity region by the well region is prepared. A silicon dioxide layer is formed in contact with the first impurity region and the well region. A gate electrode is formed on the silicon dioxide layer. A silicon-containing material is formed on the first impurity region. The silicon-containing material is oxidized. The silicon dioxide layer includes a first silicon dioxide region on the first impurity region and a second silicon dioxide region on the well region. The thickness of the first silicon dioxide region is greater than the thickness of the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved switching characteristics while suppressing a decrease in drain current, and a method of manufacturing the same can be provided.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and an electrode. The silicon carbide substrates includes a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and an intermediate impurity region, the intermediate impurity region being interposed between the third impurity region and the fourth impurity region and having an impurity concentration that is lower than the concentration of a first conductivity type impurity in the third impurity region and that is lower than the concentration of a second conductivity type impurity in the fourth impurity region. The electrode is in contact with each of the third impurity region and the fourth impurity region on the main surface of the silicon carbide substrate. The concentration of the first conductivity type impurity in the third impurity region in contact with the electrode is not less than 5×1019 cm?3.

Abstract: A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.

Abstract: There are provided a semiconductor device in which a drain leak current can be reduced in the transistor operation while high vertical breakdown voltage is achieved and a method for producing the semiconductor device. In the semiconductor device, an opening 28 that extends from an n+-type contact layer 8 and reaches an n-type drift layer 4 through a p-type barrier layer 6 is formed. The semiconductor device includes a regrown layer 27 located so as to cover portions of the p-type barrier layer 6 and the like that are exposed to the opening, the regrown layer 27 including an undoped GaN channel layer 22 and a carrier supply layer 26; an insulating layer 9 located so as to cover the regrown layer 27; and a gate electrode G located on the insulating layer 9. In the p-type barrier layer, the Mg concentration A (cm?3)and the hydrogen concentration B (cm?3) satisfy 0.1<B/A<0.9 . . . (1).

Abstract: A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.

Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. A GaN-based stacked layer 15 includes n?-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer 7. An opening 28 extends from a top layer and reaches the n?-type GaN drift layer 4. The semiconductor device includes a regrown layer 27 located so as to cover a wall surface and a bottom portion of the opening, the regrown layer 27 including an electron drift layer 22 and an electron source layer 26, a source electrode S located around the opening, a gate electrode G located on the regrown layer in the opening, and a bottom insulating layer 37 located in the bottom portion of the opening.

Abstract: A trench having a side wall and a bottom portion is formed in a silicon carbide substrate. A trench insulating film is formed to cover the bottom portion and the side wall. A silicon film is formed to fill the trench with the trench insulating film being interposed therebetween. The silicon film is etched so as to leave a portion of the silicon film that is disposed on the bottom portion with the trench insulating film being interposed therebetween. The trench insulating film is removed from the side wall. By oxidizing the silicon film, a bottom insulating film is formed. A side wall insulating film is formed on the side wall.

Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.

Abstract: In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.

Abstract: There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.

Abstract: Provided is a nitride electronic device having a structure that allows the reduction of leakage by preventing the carrier concentration from increasing in a channel layer. An inclined surface and a primary surface of a semiconductor stack extend along first and second reference planes R1, R2, respectively. The primary surface of the stack is inclined at an angle ranging from 5 to 40 degrees with respect to a reference axis indicating a c-axis direction of hexagonal group III nitride. An axis normal to the plane R1 and the axis form an angle smaller than the angle an axis normal to the plane R2 and the axis form. The oxygen concentration of the channel layer is lower than 1×1017 cm?3. It becomes possible to avoid increase in carrier concentration of the channel layer caused by the oxygen addition, thereby reducing leakage current via the channel layer in the transistor.

Abstract: A silicon carbide substrate is prepared which has a main surface covered with a silicon dioxide layer. In the silicon dioxide layer, an opening is formed by etching. In the opening, a residue resulting from the etching is on the silicon carbide substrate. The residue is removed by plasma etching in which only an inert gas is introduced. After removing the residue, under heating, a reactive gas is supplied to the silicon carbide substrate covered with the silicon dioxide layer having the opening formed therein. In this way, a trench is formed in the main surface of the silicon carbide substrate.

Abstract: The semiconductor device is formed in the form of a GaN-based stacked layer including an n-type drift layer 4, a p-type layer 6, and an n-type top layer 8. The semiconductor device includes a regrown layer 27 formed so as to cover a portion of the GaN-based stacked layer that is exposed to an opening 28, the regrown layer 27 including a channel. The channel is two-dimensional electron gas formed at an interface between the electron drift layer and the electron supply layer. When the electron drift layer 22 is assumed to have a thickness of d, the p-type layer 6 has a thickness in the range of d to 10d, and a graded p-type impurity layer 7 whose concentration decreases from a p-type impurity concentration in the p-type layer is formed so as to extend from a (p-type layer/n-type top layer) interface to the inside of the n-type top layer.

Abstract: A trench having a side wall and a bottom portion is formed in a silicon carbide substrate. A trench insulating film is formed to cover the bottom portion and the side wall. A silicon film is formed to fill the trench with the trench insulating film being interposed therebetween. The silicon film is etched so as to leave a portion of the silicon film that is disposed on the bottom portion with the trench insulating film being interposed therebetween. The trench insulating film is removed from the side wall. By oxidizing the silicon film, a bottom insulating film is formed. A side wall insulating film is formed on the side wall.

Abstract: A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained.

Abstract: A silicon carbide substrate is prepared which has a main surface covered with a silicon dioxide layer. In the silicon dioxide layer, an opening is formed by etching. In the opening, a residue resulting from the etching is on the silicon carbide substrate. The residue is removed by plasma etching in which only an inert gas is introduced. After removing the residue, under heating, a reactive gas is supplied to the silicon carbide substrate covered with the silicon dioxide layer having the opening formed therein. In this way, a trench is formed in the main surface of the silicon carbide substrate.

Abstract: A substrate product is disposed in a growth furnace at time t0, and the substrate temperature is then raised to 950° C. At time t3 after the substrate temperature is sufficiently stable, trimethyl gallium and ammonia are supplied to the growth furnace, to grow an i-GaN film. The substrate temperature reaches 1080° C. at time t5. At time t6 after the substrate temperature is sufficiently stable, trimethyl gallium, trimethyl aluminum and ammonia are supplied to the growth furnace, to grow an i-AlGaN film. Supply of trimethyl gallium and trimethyl aluminum is stopped at time t7 to discontinue film deposition. Quickly thereafter, supply of ammonia and hydrogen to the growth furnace is stopped and supply of nitrogen is initiated, to change the atmosphere of ammonia and hydrogen in a growth furnace chamber to a nitrogen atmosphere. After formation of the nitrogen atmosphere, the substrate temperature starts being lowered at time t8.

Abstract: A first layer of a first conductivity type made of silicon carbide is formed. A second layer of a second conductivity type different from the first conductivity type positioned on the first layer, and a third layer of the first conductivity type positioned on the second layer are formed. The step of forming second and third layers includes the steps of performing impurity ion implantation, and performing heat treatment for activating impurities implanted by the impurity ion implantation. After the step of performing heat treatment, a trench having a side wall penetrating the third layer and the second layer and having a bottom reaching the first layer is formed. A gate insulating film to cover the side wall of the trench is formed. As a result, a silicon carbide semiconductor device having a low ON resistance is provided.

Abstract: A method for manufacturing a heterojunction field effect transistor 1 comprises the steps of: epitaxially growing a drift layer 20a on a support substrate 10; epitaxially growing a current blocking layer 20b which is a p-type semiconductor layer on the drift layer 20a at a temperature equal to or higher than 1000° C. by using hydrogen gas as a carrier gas; and epitaxially growing a contact layer 20c on the current blocking layer 20b by using at least one gas selected from the group consisting of nitrogen gas, argon gas, helium gas, and neon gas as a carrier gas.