Patents by Inventor Yu-Te Hsieh

Yu-Te Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230025520
    Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.
    Type: Application
    Filed: August 2, 2022
    Publication date: January 26, 2023
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yu-Te HSIEH, I-Lin CHU
  • Patent number: 11508776
    Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: November 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Larry Kinsman, Yusheng Lin, Yu-Te Hsieh, Oswald Skeete, Weng-Jin Wu, Chi-Yao Kuo
  • Patent number: 11476292
    Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: October 18, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te Hsieh
  • Patent number: 11444111
    Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: September 13, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yu-Te Hsieh, I-Lin Chu
  • Publication number: 20220223641
    Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, at least one conductor connected to the image sensor die and the substrate, and a light-transmitting member including a substrate member, a first leg member extending from a first edge portion of the substrate member, and a second leg member extending from a second edge portion of the substrate member, the first leg member being coupled to the substrate, the second leg member being coupled to the substrate.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 14, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Larry Duane KINSMAN, Yu-Te HSIEH
  • Publication number: 20220216255
    Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, a light-transmitting member, an inner joint member disposed between the light-transmitting member and the image sensor die, and an outer joint member disposed between the light-transmitting member and the substrate.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 7, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH
  • Publication number: 20220020800
    Abstract: According to an aspect, a method for fabricating an image sensor package to define a gap height includes coupling an image sensor die to a substrate, forming a plurality of pillar members on the image sensor die, dispensing a bonding material on the image sensor die, contacting a transparent member with the bonding material such that a height of the pillar members defines a gap height between an active region of the image sensor die and the transparent member, and curing the bonding material to couple the transparent member to the image sensor die.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 20, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH
  • Publication number: 20210305301
    Abstract: Implementations of semiconductor packages may include: a substrate having a first side and a second side and a die having an active area on a second side of the die. A first side of the die may be coupled to the second side of the substrate. The semiconductor package may also include a glass lid having a first side and a second side. The glass lid may be coupled over a second side of the die. The semiconductor package may include a first and a second molding compound and one or more cushions positioned between a first side of the glass lid and a portion of the first molding compound. The second molding compound may be coupled to the substrate and the around the die and the glass lid.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH
  • Patent number: 11037970
    Abstract: Implementations of semiconductor packages may include: a substrate having a first side and a second side and a die having an active area on a second side of the die. A first side of the die may be coupled to the second side of the substrate. The semiconductor package may also include a glass lid having a first side and a second side. The glass lid may be coupled over a second side of the die. The semiconductor package may include a first and a second molding compound and one or more cushions positioned between a first side of the glass lid and a portion of the first molding compound. The second molding compound may be coupled to the substrate and the around the die and the glass lid.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 15, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te Hsieh
  • Publication number: 20200335544
    Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH
  • Publication number: 20200312897
    Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 1, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yu-Te HSIEH, I-Lin CHU
  • Patent number: 10790208
    Abstract: Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 29, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te Hsieh
  • Patent number: 10714454
    Abstract: According to an aspect, a stack packaging structure includes a substrate, a semiconductor device coupled to a surface of the substrate, an image sensor device coupled to the semiconductor device such that the semiconductor device is disposed between the surface of the substrate and the image sensor device, at least one bond wire connected to the image sensor device and the surface of the substrate, a inner molding disposed between the surface of the substrate and the image sensor device, where the semiconductor device is encapsulated within the inner molding, and an outer molding disposed on the surface of the substrate, where the at least one bond wire is encapsulated within the outer molding.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 14, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Yu-Te Hsieh
  • Patent number: 10707257
    Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 7, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Yu-Te Hsieh
  • Publication number: 20200144318
    Abstract: Implementations of semiconductor packages may include: a substrate having a first side and a second side and a die having an active area on a second side of the die. A first side of the die may be coupled to the second side of the substrate. The semiconductor package may also include a glass lid having a first side and a second side. The glass lid may be coupled over a second side of the die. The semiconductor package may include a first and a second molding compound and one or more cushions positioned between a first side of the glass lid and a portion of the first molding compound. The second molding compound may be coupled to the substrate and the around the die and the glass lid.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 7, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH
  • Publication number: 20200058618
    Abstract: According to an aspect, a stack packaging structure includes a substrate, a semiconductor device coupled to a surface of the substrate, an image sensor device coupled to the semiconductor device such that the semiconductor device is disposed between the surface of the substrate and the image sensor device, at least one bond wire connected to the image sensor device and the surface of the substrate, a inner molding disposed between the surface of the substrate and the image sensor device, where the semiconductor device is encapsulated within the inner molding, and an outer molding disposed on the surface of the substrate, where the at least one bond wire is encapsulated within the outer molding.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH
  • Publication number: 20200058695
    Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH
  • Publication number: 20190229144
    Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.
    Type: Application
    Filed: April 3, 2019
    Publication date: July 25, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Larry KINSMAN, Yusheng LIN, Yu-Te HSIEH, Oswald SKEETE, Weng-Jin WU, Chi-Yao KUO
  • Publication number: 20190229025
    Abstract: Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.
    Type: Application
    Filed: April 3, 2019
    Publication date: July 25, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH
  • Publication number: 20190172861
    Abstract: Implementations of semiconductor packages may include: a substrate, a die electrically coupled to the substrate, and a wall coupled to the substrate wall. The wall may extend around a perimeter of the die. The wall may include a molding dam formed therein. The semiconductor package may also include a glass lid coupled to the wall and the molding dam. A mold compound may be coupled into the molding dam and across a thickness of the glass lid.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH