Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Abstract: A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path.

Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Abstract: According to an embodiment, a semiconductor device is provided. The device includes a second region having a greater curvature than a first region. The device includes an epitaxy layer of a first conductivity type, a well of a second conductivity type in the epitaxy layer, a drain in the epitaxy layer, a source in the well, and a bulk in the well and in contact with the source, the bulk having a greater area in the second region than in the first region.

Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

Abstract: According to an embodiment, a semiconductor device is provided. The device includes: The second region has a greater curvature than the first region. The device includes: an N-type epitaxy layer; a P-well in the N-type epitaxy layer; a drain in the N-type epitaxy layer; a source in the P-well; and a bulk in the P-well and in contact with the source, wherein the bulk has a greater area in the second region than in the first region.

Abstract: One or more electrostatic discharge (ESD) control circuit are disclosed herein. In an embodiment, an ESD control circuit has first and second trigger transistors, first and second ESD transistors, and first and second feedback transistors. The ESD transistors provide ESD current paths for ESD current generated during an ESD event. The first and second trigger transistors are on during normal operation to maintain the ESD transistors in an off state. During an ESD event, the first and second transistors are turned off to enable the first and second ESD transistors to provide ESD current paths. The first and second feedback transistors turn on during an ESD event to reinforce the on state of the ESD transistors and to reinforce the off state of the trigger transistors. In this way, the ESD control circuit stably provides multiple ESD current paths to discharge ESD current.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

Abstract: According to an embodiment, a semiconductor device is provided. The device includes: The second region has a greater curvature than the first region. The device includes: an N-type epitaxy layer; a P-well in the N-type epitaxy layer; a drain in the N-type epitaxy layer; a source in the P-well; and a bulk in the P-well and in contact with the source, wherein the bulk has a greater area in the second region than in the first region.

Abstract: In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.

Abstract: A method of making a circuit device includes forming core circuitry. The core circuitry includes a doped region in the core circuit. The method further includes implanting a first set of guard rings around a periphery of the core circuitry. The first set of guard rings has a first dopant type. Implanting the first set of guard rings includes implanting the first set of guard rings spaced from the doped region. The method further includes implanting a second set of guard rings having a second dopant type, wherein the second dopant type being opposite to the first dopant type. At least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings.

Abstract: According to an embodiment, a semiconductor device is provided. The device includes: The second region has a greater curvature than the first region. The device includes: an N-type epitaxy layer; a P-well in the N-type epitaxy layer; a drain in the N-type epitaxy layer; a source in the P-well; and a bulk in the P-well and in contact with the source, wherein the bulk has a greater area in the second region than in the first region.

Abstract: In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.

Abstract: A circuit device includes core circuitry. The circuit device further includes a first set of guard rings having a first dopant type, the first set of guard rings being around a periphery of the core circuitry, the first set of guard rings comprising a first guard ring and a second guard ring. The circuit device further includes a second set of guard rings having a second dopant type, the second dopant type being opposite to the first dopant type, wherein at least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings, and the second set of guard rings comprises a third guard ring and a fourth guard ring.

Abstract: According to an embodiment, a semiconductor device is provided. The device includes: The second region has a greater curvature than the first region. The device includes: an N-type epitaxy layer; a P-well in the N-type epitaxy layer; a drain in the N-type epitaxy layer; a source in the P-well; and a bulk in the P-well and in contact with the source, wherein the bulk has a greater area in the second region than in the first region.

Abstract: A circuit includes a driver circuit between a first and second power supply nodes, and a first and second electrostatic discharge (ESD) protection circuits. The driver circuit is configured to generate a pair of differential signals at a first output node and a second output node. The first ESD protection circuit is coupled between the first output node and the second power supply node. The first ESD protection circuit includes a first transistor, and the first transistor includes a drain region and a source region in a well region. The second ESD protection circuit is coupled between the second output node and the second power supply node. The second ESD protection circuit includes a second transistor, and the second transistor includes a drain region and a source region in the well region.

Abstract: An electrostatic discharge (ESD) protection device is disclosed, which includes a substrate of a positive dopant type; a p-well defined in the substrate; a depletion inducing structure of a negative dopant type having a gap defined in a bottom portion thereof disposed in the p-well, and a n-channel device disposed in a planar encircled region defined by the depletion inducing structure. The well region is in connection with the substrate through the depletion inducing structure. Upon an ESD stress, the depletion inducing structure induces an expanded depletion region in the substrate under the well region, thus providing a substrate trigger mechanism that reduces the triggering voltage of the ESD protection device.