Abstract: A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), the UE receives one or more signals indicative of a first Physical Uplink Shared Channel (PUSCH) and a second PUSCH on a first cell and in a Transmission Time Interval (TTI). The UE determines to transmit a first Uplink Control Information (UCI) in the TTI, wherein the first UCI overlaps with the first PUSCH and the second PUSCH in time domain. The UE selects the first PUSCH for multiplexing the first UCI based on whether the UE is configured with joint Hybrid Automatic Repeat Request (HARQ) feedback mode or separate HARQ feedback mode. The UE transmits the first PUSCH and the second PUSCH on the first cell, wherein the first PUSCH transmitted on the first cell includes the first UCI.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: Embodiments of the present disclosure relate to zeolites and method for making such zeolites. According to embodiments disclosed herein, a zeolite may have a microporous framework including a plurality of micropores having diameters of less than or equal to 2 nm and a plurality of mesopores having diameters of greater than 2 nm and less than or equal to 50 nm. The microporous framework may include an MFI framework type. The microporous framework may include silicon atoms, aluminum atoms, oxygen atoms, and transition metal atoms. The transition metal atoms may be dispersed throughout the entire microporous framework.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A package structure, including a circuit board, multiple circuit structure layers, at least one bridge structure, and at least one supporting structure, is provided. The circuit structure layer is disposed on the circuit board. The bridge structure is connected between the two adjacent circuit structure layers. The supporting structure is located between the two adjacent circuit structure layers, and the supporting structure has a first end and a second end opposite to each other and respectively connecting the bridge structure and the circuit board.

Abstract: A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are located on the second surface. The second contact layer is located below the first surface. The active layer is located between the first contact layer and the second contact layer. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and is electrically connected the first surface of the first contact layer. The second electrode is located on the passivation layer and is electrically connected to the second contact layer.

Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.

Abstract: Disclosed are calibration techniques that can be implemented by a device that conducts biological tests. In certain embodiments, the device for testing a biological specimen includes a receiving mechanism to receive a carrier, a camera module arranged to capture imagery of the carrier, and a processor. Some examples of the processor can detect a calibration mode trigger. In calibration mode, the processor can divide the captured imagery into segments and selectively perform one or more calibration procedures for each segment. Then, the processor records a calibration result for each segment.

Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a second dielectric layer on the high resistance layer, a low-k dielectric layer over the second dielectric layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.

Abstract: An electronic device and a forming method thereof are provided. The electronic device includes a substrate, a metal layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer. The metal layer is disposed on the substrate and includes a sensing line and a drain electrode. The first insulating layer is disposed on the metal layer. The first conductive layer is disposed on the first insulating layer and includes a touch electrode. The second insulating layer is disposed on the first conductive layer. The second conductive layer is disposed on the second insulating layer and includes a conductive pattern. The conductive pattern is electrically connected to the sensing line and the touch electrode.

Abstract: A method for producing ?-aminobutyric acid includes cultivating, in a culture medium containing glutamic acid or a salt thereof, a probiotic composition including at least one lactic acid bacterial strain selected from the group consisting of Bifidobacterium breve CCFM1025 which is deposited at the Guangdong Microbial Culture Collection Center under an accession number GDMCC 60386, Lactobacillus acidophilus TYCA06, Lactobacillus plantarum LPL28, and Bifidobacterium longum subsp. infantis BLI-02 which are deposited at the China General Microbiological Culture Collection Center respectively under accession numbers CGMCC 15210, CGMCC 17954, and CGMCC 15212, Lactobacillus salivarius subsp. salicinius AP-32 which is deposited at the China Center for Type Culture Collection under an accession number CCTCC M 2011127, and combinations thereof.

Abstract: A method and apparatus of Inter prediction for video coding using Multi-hypothesis (MH) are disclosed. If an MH mode is used for the current block: at least one MH candidate is derived using reduced reference data by adjusting at least one coding-control setting; an Inter candidate list is generated, where the Inter candidate list comprises said at least one MH candidate; and current motion information associated with the current block is encoded using the Inter candidate list at the video encoder side or the current motion information associated with the current block is decoded at the video decoder side using the Merge candidate list. The coding control setting may correspond to prediction direction setting, filter tap setting, block size of reference block to be fetched, reference picture setting or motion limitation setting.

Abstract: An image sensor device and methods of forming an image sensor device are provided. The image sensor device includes a plurality of image-sensing elements arranged within the device substrate. The image sensor device further includes an isolation grid structure extending into the device substrate and made up of a plurality of isolation grid segments that surround the outer perimeters of the plurality of image-sensing elements. The isolation grid structure includes a passivation liner and a conductive material in contact with the passivation liner. The conductive material may be an indium-tin-oxide film.

Abstract: The present invention discloses a blind slat positioning device and a window blind thereof. The positioning device can fix the slat at any height at which the slat is pulled down. The positioning device includes a turning seat which is provided at least with an overbend element for a pull cord to wrap around. The overbend element includes at least a ridge, resulting an effect that the slat stops at the height at which the slat is pulled down, with the aid of gravity.

Abstract: An electronic device having a substrate includes a substrate and at least one outer layer. The substrate has a plurality of first vias. The outer layer has a plurality of second vias. The outer layer is disposed on a side of the substrate. The first vias have a larger distribution density or quantity than the second vias so that a portion of the first vias are electrically connected to the second vias, and a portion of the first vias are electrically floating.

Abstract: An electronic device includes a via-array substrate, an outer layer, and an alignment substrate. The via-array substrate has a plurality of first vias. The outer layer has a plurality of second vias and is disposed on a side of the via-array substrate. The first vias are greater in distribution density or quantity than the second vias. A part of the first vias is electrically connected to the second vias, and another part of the first vias is electrically floating. The alignment substrate includes a core layer disposed on the outer layer, a plurality of conductive traces, a plurality of interconnecting pads, and a plurality of alignment mark pads. The conductive traces are disposed in the core layer. The interconnecting pads and the alignment mark pads are disposed on a surface of the core layer located away from the outer layer. A part of the conductive traces electrically connects a part of the interconnecting pads and a part of the first vias.

Abstract: This disclosure provides a conductive circuit carrier module including a carrier and a conductive circuit film layer. The conductive circuit film layer is disposed on the carrier. The conductive circuit film layer has at least one conductive circuit structure including a vertical wire part and at least four horizontal wire parts. The vertical wire part extends along a thickness direction of the conductive circuit film layer. The at least four horizontal wire parts are connected to one another via the vertical wire part and extend along a direction substantially perpendicular to the vertical wire part. The at least four horizontal wire parts are symmetrically arranged or asymmetrically arranged with respect to the vertical wire part.