Abstract: A flip chip package structure is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

Abstract: A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

Abstract: A semiconductor package structure includes a semiconductor component, a substrate, solder bumps, underfill, a buffer means, and solder balls. The substrate is under the semiconductor component. A joint area is formed between the first surface of the semiconductor and the upper surface of the substrate. Several solder bumps are disposed in the joint area, for electrically connecting the semiconductor component and the substrate. The underfill is filled in the joint area, for coating the solder bumps and tightly jointing the semiconductor component and the substrate. The buffer means is situated in the jointing area, for buffering the underfill to be confined in the joint area. Several solder balls are disposed on the lower surface of the substrate.

Abstract: A plasma display panel with a plurality of non-transparent display electrode pairs and a method of forming the same. Each electrode of every non-transparent display electrode pair is separated from but close to one another for effective discharging. For effective displaying, it is necessary that the area of the non-transparent display electrodes is smaller than the area of the panel. In the present invention, the shape of the non-transparent display electrodes are manufactured in a shape with a plurality of openings, such as a ladder or a chain.

Abstract: A flip chip package structure comprising a chip, a substrate, at least a first bump and a plurality of second bumps is provided. The chip has a first bump-positioning region and the substrate has a second bump-positioning region. The substrate has at least a first hole and multiple second holes. The first hole and the second holes are located within the second bump-positioning region. The first hole has a depth greater than that of the second hole. The first bump is set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The first bump is bonded to the substrate through the first holes. The second bumps are set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The second bumps are bonded to the substrate through the second holes. The first bump has a volume greater than the volume of the second bump.

Abstract: A chip package structure includes a substrate having an upper surface and a lower surface, a chip having an active surface and a back surface, a stiffener, a first heat sink and a second heat sink. The active surface of the chip is attached on the upper surface of the substrate via bumps, so that the chip electrically connects to the substrate. The stiffener is disposed on the upper surface of the substrate and around the chip. The first heat sink is disposed on the back surface of the chip and on the stiffener ring. The second heat sink is disposed on the lower surface of the substrate.

Abstract: A flip-chip substrate for bonding with a chip is provided. The chip has an active surface with a plurality of bonding pads and each bonding pad has a bump thereon. The flip-chip substrate has a plurality of contact pads that correspond in positions with the bonding pads on the chip such that the chip pads are aligned to their corresponding contact pads at the melting point of the bump material.

Abstract: A flip chip packaging process uses an underfill as an encapsultant to reduce the possibility of delamination from occurring due to differential coefficients of thermal expansion, and thus the reliability of a flip chip package structure can be increased. Furthermore, the flooding of the encapsulant over the cutting line need not be taken into consideration for cutting the substrate. Therefore, the usage area of the substrate usage is increased, i.e., more chips can be mounted per unit area of the substrate.

Abstract: A manufacturing method of a flip chip package mainly comprises the following steps. Initially, a chip having an active surface with a plurality of bumps formed thereon is provided. Next, the active surface of the chip is faced to and disposed on an upper surface of a substrate. In such manner, the chip will be electrically connected to the substrate and a gap between the chip and the substrate will be formed. Afterwards, an underfill is filled in the gap and then a first curing process is performed to have the underfill partially hardened to have the underfill transformed into a partially hardened underfill. Finally, the combination of the chip, the substrate and the partially hardened underfill is flipped over to have the substrate located above the chip, then a second curing process is performed to have the partially hardened underfill into a fully hardened underfill, and then flipping over the combination of the chip, the substrate and the fully hardened underfill.

Abstract: The present invention provides a flip chip package structure comprising a substrate, a chip and a plurality ofbumps. A plurality of contacts is disposed on the carrying surface and the chip is disposed on the carrying surface of the substrate. The chip includes an active surface and a plurality of bonding pads. The active surface of the chip comprises a bumping region and a plurality of non-bumping regions at corners of the chip, while the bonding pads are disposed within the bumping region of the active surface of the chip. The bumps, respectively disposed on the bonding pads, electrically and mechanically connect the contacts and the bonding pads.

Abstract: A semiconductor package structure includes a semiconductor component, a substrate, solder bumps, underfill, a buffer means, and solder balls. The substrate is under the semiconductor component. A joint area is formed between the first surface of the semiconductor and the upper surface of the substrate. Several solder bumps are disposed in the joint area, for electrically connecting the semiconductor component and the substrate. The underfill is filled in the joint area, for coating the solder bumps and tightly jointing the semiconductor component and the substrate. The buffer means is situated in the jointing area, for buffering the underfill to be confined in the joint area. Several solder balls are disposed on the lower surface of the substrate.

Abstract: A chip package structure includes a substrate having an upper surface and a lower surface, a chip having an active surface and a back surface, a stiffener, a first heat sink and a second heat sink. The active surface of the chip is attached on the upper surface of the substrate via bumps, so that the chip electrically connects to the substrate. The stiffener is disposed on the upper surface of the substrate and around the chip. The first heat sink is disposed on the back surface of the chip and on the stiffener ring. The second heat sink is disposed on the lower surface of the substrate.

Abstract: A manufacturing method of a flip chip package mainly comprises the following steps. Initially, a chip having an active surface with a plurality of bumps formed thereon is provided. Next, the active surface of the chip is faced to and disposed on an upper surface of a substrate. In such manner, the chip will be electrically connected to the substrate and a gap between the chip and the substrate will be formed. Afterwards, an underfill is filled in the gap and then a first curing process is performed to have the underfill partially hardened to have the underfill transformed into a partially hardened underfill. Finally, the combination of the chip, the substrate and the partially hardened underfill is flipped over to have the substrate located above the chip, then a second curing process is performed to have the partially hardened undefill into a fully hardened underfill, and then flipping over the combination of the chip, the substrate and the fully hardened underfill.

Abstract: A face-to-face multi-chip flip-chip package includes a first chip, at least a second chip and a package substrate. The package substrate has a top surface, a bottom surface and a concave wall between the top surface and the bottom surface. The second chip is flip-chip mounted on active surface of the first chip. The first chip is mounted on the package substrate so that the second chip is placed inside a chip accommodation space of the package substrate which is defined by the concave wall. A side surface of the second chip is a progressive distance from the chip accommodation space for lessening capillary flow of underfilling material between the concave wall of the package substrate and the side surface of the second chip during dispensing the underfilling material.

Abstract: A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

Abstract: A multi-chips stacked package comprises a substrate, an upper chip, a lower chip, a dam, a heat spreader, an underfill, a plurality of first electrically conductive bumps and a plurality of second electrically conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate and the second chip is accommodated in the opening and flip-chip bonded to the upper chip. Furthermore, the dam is disposed on the substrate and supports the heat spreader so as to fix the heat spreader to the back surface of the first chip. In addition, the underfill is filled into the space which is enclosed by the dam, the upper surface of the substrate and the heat spreader. In such a manner, at least the upper chip, the lower chip, the first and second electrically conductive bumps and a portion of the substrate are covered by the underfill.

Abstract: A flip chip package comprises a carrier, a chip, a dam, a heat spreader, an underfill and a plurality of electrically conductive bumps. The chip is flip-chip bonded to the upper surface of the carrier. Furthermore, the dam is disposed on the carrier and supports the heat spreader. In addition, the underfill is filled into the space that is enclosed by the dam. In such a manner, the chip, the electrically conductive bumps and a portion of the carrier are covered by the underfill. The underfill is connected to the dam, the heat spreader and the carrier simultaneously, so the reinforced structure including the heat spreader, the underfill and the dam can reduce the stress at the interconnection between the chip and carrier so as to prevent the bumps connecting the chip and the carrier from being damaged.

Abstract: A method and structure for broadening cholesteric liquid crystals spectrum are described. An electrode structure is added on a side of cholesteric liquid crystals, for producing a fringe field which is perpendicular to a screw axis of the cholesteric liquid crystal. Hence, the thread pitches of cholesteric liquid crystals near the electrode structure are lengthened, but the other thread pitches of cholesteric liquid crystals far from the electrode structure remain the same. Besides, light having appropriate wavelength is used to congeal the cholesteric liquid crystals having a polymeric characteristic, so that the cholesteric liquid crystals have varied thread pitches while no voltage is applied to the electrode structure. Therefore, the spectrum of cholesteric liquid crystals and applications thereof are widened.

Abstract: The pla sma display panel has some pairs of non-transparent discharge electrodes. Herein, no transparent discharge electrode is desired. Herein, for each pair, the non-transparent discharge electrodes are separated but closed to effectively discharge. Besides, the area of the non-transparent discharge electrodes is clearly smaller than the area of the panel. Furthermore, the shape of each non-transparent discharge electrode is alike to a shape with some openings, such as ladder or chain.

Abstract: A flip chip package structure comprising a chip, a substrate, at least a first bump and a plurality of second bumps is provided. The chip has a first bump-positioning region and the substrate has a second bump-positioning region. The substrate has at least a first hole and multiple second holes. The first hole and the second holes are located within the second bump-positioning region. The first hole has a depth greater than that of the second hole. The first bump is set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The first bump is bonded to the substrate through the first holes. The second bumps are set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The second bumps are bonded to the substrate through the second holes. The first bump has a volume greater than the volume of the second bump.