Abstract: A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A hard mask is deposited over the conductive layer and patterned using photolithography techniques. The photoresist material is removed prior to etching the underlying conductive layer and dielectric layer. The hard mask is also used as an implant mask. Another mask may be deposited and formed over the conductive layer to form other devices in other regions of the substrate. The other mask is preferably removed from over the hard mask prior to etching the conductive layer and the dielectric layer.

Abstract: A group authentication method adaptable to a communication system is disclosed. The communication system includes a user group, a serving network, and a home network. The user group includes at least one mobile station. The home network pre-distributes a group authentication key to itself and all the mobile stations in the same user group and generates a mobile station authentication key for each mobile station. The home network generates a group list for recording related information of the user group. The home network has a database for recording the group list. The serving network has a database for recording the group list and a group authentication data received from the home network. The group authentication method includes following steps. The serving network performs an identification action to a mobile station. The communication system performs a full authentication action or a local authentication action according to the result of the identification action.

Abstract: A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer.

Abstract: Goldcatalyst Goldcatalyst comprising gold on a support of ceria or ceria-manganese oxide is used for the oxidation of CO in a H2 stream.

Abstract: This present invention provides the preparation of a manganese oxide-ferric oxide-supported nano-gold catalyst and a process for subjecting carbon monoxide and oxygen to interaction resulting in the formation of carbon dioxide in a hydrogen-rich environment by a manganese oxide-ferric oxide-supported nano-gold catalyst to remove carbon monoxide in hydrogen stream. The size of the nano-gold particle is less than 5 nm and supported on mixed oxides MnO2/Fe2O3 in various molar ratios. Preferential oxidation of CO in the presence of CO, O2 and H2 by the manganese oxide-ferric oxide-supported nano-gold catalyst is carried out in a fixed-bed reactor in the process of the present invention. The O2/CO molar ratio is in the range of 0.5 to 4. The manganese oxide-ferric oxide-supported nano-gold catalyst of the present invention is applied to reduce CO concentration in hydrogen steam to less than 100 ppm to prevent CO from contaminating the electrodes of a fuel cell.

Abstract: A method for manufacturing semiconductor packages is provided. The upper surface of a substrate has a plurality of slots and surface mount devices are positioned across the slots. In this circumstance, the space below the surface mount devices can be filled up with sealant as a result of the arrangement of the slots. This can avoid the occurrence of the melted solders to bridge to each other and of the tomb stone effect of the surface mount devices.

Abstract: This present invention provides the preparation of a manganese oxide-cerium oxide-supported nano-gold catalyst and a process for subjecting carbon monoxide and oxygen to interaction resulting in the formation of carbon dioxide in a hydrogen-rich environment by a manganese oxide-cerium oxide-supported nano-gold catalyst to remove carbon monoxide in hydrogen stream. The size of the nano-gold particle is less than 5 nm and supported on mixed oxides MnO2/CeO2 in various molar ratios. Preferential oxidation of CO in the presence of CO, O2 and H2 by the manganese oxide-cerium oxide-supported nano-gold catalyst is carried out in a fixed-bed reactor in the process of the present invention. The CO/O2 molar ratio is in the range of 0.5 to 3. The manganese oxide-cerium oxide-supported nano-gold catalyst of the present invention is applied to reduce CO concentration in hydrogen steam to less than 100 ppm to prevent CO from contaminating the electrodes of a fuel cell.

Abstract: A hydrogenation process of chloronitrobenzene. The hydrogenation process comprises the steps of producing a nanosized boron-containing nickel catalyst, wherein a ratio of the amount of the boron atom to the amount of the nickel atom in the nanosized boron-containing nickel catalyst is of about 0.1-0.9. Then, the nanosized boron-containing nickel catalyst is placed into a reactor with a chloronitrobenzene an alcohol solvent having carbon number less than four per molecule and a hydrogenation process is performed to hydrogenating the chloronitrobenzene in hydrogen with a reaction pressure of about 5-40 atm and a reaction temperature of about 40-150° C.

Abstract: Dextrorotatory morphinan derivatives of formula (I) or pharmaceutically acceptable salts thereof were found to have local anesthetic effects: wherein R and R? are independently selected from hydrogen and a methyl group, and at least one of R and R? is a methyl group. The dextrorotatory morphinan derivatives of formula (I) or pharmaceutically acceptable salts thereof can therefore be used in the manufacture of pharmaceutical compositions for local anesthesia that may provide a safe and prolonged local anesthetic effect.

Abstract: A hydrogenation process of chloronitrobenzene. The hydrogenation process comprises the steps of producing a nanosized boron-containing nickel catalyst, wherein a ratio of the amount of the boron atom to the amount of the nickel atom in the nanosized boron-containing nickel catalyst is of about 0.1-0.9. Then, the nanosized boron-containing nickel catalyst is placed into a reactor with a chloronitrobenzene an alcohol solvent having carbon number less than four per a molecular and a hydrogenation process is performed to hydrogenating the chloronitrobenzene in hydrogen with a reaction pressure of about 5-40 atm and a reaction temperature of about 40-150° C.

Abstract: A method for preparing for a photocatalyst. The method comprises steps of providing a mixture of indium oxide and vanadium oxide and then calcinning the mixture to obtain a indium vanadium quadrioxide. Further, a nickel nitrate solution is added to the indium vanadium quadrioxide to form a catalyst with a nickel oxide supported amount of about 0.1-2.0 wt. % and a post treatment is performed on the catalyst. In the post treatment, a reduction process is performed and then an oxidation process is performed.

Abstract: A flip chip packaging process uses an underfill as an encapsultant to reduce the possibility of delamination from occurring due to differential coefficients of thermal expansion, and thus the reliability of a flip chip package structure can be increased. Furthermore, the flooding of the encapsulant over the cutting line need not be taken into consideration for cutting the substrate. Therefore, the usage area of the substrate usage is increased, i.e., more chips can be mounted per unit area of the substrate.

Abstract: A flip chip package structure is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

Abstract: A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

Abstract: A semiconductor package structure includes a semiconductor component, a substrate, solder bumps, underfill, a buffer means, and solder balls. The substrate is under the semiconductor component. A joint area is formed between the first surface of the semiconductor and the upper surface of the substrate. Several solder bumps are disposed in the joint area, for electrically connecting the semiconductor component and the substrate. The underfill is filled in the joint area, for coating the solder bumps and tightly jointing the semiconductor component and the substrate. The buffer means is situated in the jointing area, for buffering the underfill to be confined in the joint area. Several solder balls are disposed on the lower surface of the substrate.

Abstract: A plasma display panel with a plurality of non-transparent display electrode pairs and a method of forming the same. Each electrode of every non-transparent display electrode pair is separated from but close to one another for effective discharging. For effective displaying, it is necessary that the area of the non-transparent display electrodes is smaller than the area of the panel. In the present invention, the shape of the non-transparent display electrodes are manufactured in a shape with a plurality of openings, such as a ladder or a chain.

Abstract: A flip chip package structure comprising a chip, a substrate, at least a first bump and a plurality of second bumps is provided. The chip has a first bump-positioning region and the substrate has a second bump-positioning region. The substrate has at least a first hole and multiple second holes. The first hole and the second holes are located within the second bump-positioning region. The first hole has a depth greater than that of the second hole. The first bump is set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The first bump is bonded to the substrate through the first holes. The second bumps are set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The second bumps are bonded to the substrate through the second holes. The first bump has a volume greater than the volume of the second bump.