Patents by Inventor Yu-Wen Huang

Yu-Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250114867
    Abstract: A laser welding method for steel plates and a profile steel welded by laser welding are disclosed. The laser welding method comprises the following steps of connecting a first steel plate and a second steel plate to form a joint; and using a laser to weld the joint to form a profile steel. The laser has a laser power between 10,000 and 25,000 watts. A weld bead is formed at the joint. The weld bead has a weld depth and a weld width. The ratio of the weld depth to the weld width is between 1 and 5. Thus, the process can be simplified effectively, the welding time can be shortened, and the processing area can be reduced.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Inventors: LI-WEN LAI, WEI-LUN TSAI, YU-PING HUANG, CHIH-HUI TAI
  • Publication number: 20250120077
    Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 10, 2025
    Inventors: Der-Tsyr Fan, l-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng, Chen-Ming Tsai, l-Chun Chuang
  • Publication number: 20250113828
    Abstract: Present invention teaches the method of using a keratin hydrolysis peptide (“KHP”) solution to improve the efficacy of fertilizer usage and absorption by cotton plants. By selectively choosing specific weights of feathers and water, and treating the mixture to a high-temperature high-pressure hydrolysis process, the resulting solution is confirmed to contain at least 253 peptides and then infused to the fertilized soil in which the cotton seeds are planted and grown. Optionally, the KHP solution can be diluted by water, as disclosed in the specification, for applying to the fertilized soil around the cotton plants.
    Type: Application
    Filed: January 11, 2024
    Publication date: April 10, 2025
    Applicant: CH Biotech R&D Co., Ltd.
    Inventors: Jenn Wen HUANG, Yi-Chiao CHAN, Yu-Yi WU, Nai-Hua YE
  • Patent number: 12272600
    Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Wen Chen, Chang-Ting Chung, Yi-Hsiang Chao, Yu-Ting Wen, Kai-Chieh Yang, Yu-Chen Ko, Peng-Hao Hsu, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20250112049
    Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Inventors: Chia-Cheng CHAO, Hsin-Chieh HUANG, Yu-Wen WANG
  • Patent number: 12264972
    Abstract: A vertically integrated micro-bolometer includes an integrated circuit chip, an infrared sensing film, and a metal bonding layer. The integrated circuit chip includes a silicon substrate, a circuit element, and a dielectric layer disposed on the silicon substrate. The infrared sensing film includes a top absorbing layer, a sensing layer, and a bottom absorbing layer. The sensing layer is disposed between the top absorbing layer and the bottom absorbing layer. Materials of the top absorbing layer, the sensing layer, and the bottom absorbing layer are materials compatible with a semiconductor manufacturing process. The metal bonding layer connects the dielectric layer on the silicon substrate in the integrated circuit chip and the bottom absorbing layer of the infrared sensing film to form a vertically integrated micro-bolometer. In one embodiment, the infrared sensing film is divided into a central sensing film, a surrounding sensing film, and a plurality of connecting portions by a plurality of slots.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: April 1, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Wen Hsu, Lu-Pu Liao, Chao-Ta Huang, Bo-Kai Chao
  • Publication number: 20250098179
    Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Inventors: Abhishek A. Sharma, Van H. Le, Fatih Hamzaoglu, Juan G. Alzate-Vinasco, Nikhil Jasvant Mehta, Vinaykumar Hadagali, Yu-Wen Huang, Honore Djieutedjeu, Tahir Ghani, Timothy Jen, Shailesh Kumar Madisetti, Jisoo Kim, Wilfred Gomes, Kamal Baloch, Vamsi Evani, Christopher Wiegand, James Pellegren, Sagar Suthram, Christopher M. Pelto, Gwang Soo Kim, Babita Dhayal, Prashant Majhi, Anand Iyer, Anand S. Murthy, Pushkar Sharad Ranade, Pooya Tadayon, Nitin A. Deshpande
  • Publication number: 20250098555
    Abstract: A spatial light modulator device includes an array of spatial light modulator cells located over a substrate. Each of the spatial light modulator cells includes: a layer stack including a phase change material plate, a spacer dielectric material plate that underlies the phase change material plate, and a metallic heater plate underlying the spacer dielectric material plate and including outer sidewalls; and a pair of bottom electrode via structures contacting a respective surface segment of a bottom surface of the metallic heater plate. Each of the outer sidewalls of the metallic heater plate is vertically coincident with a respective sidewall of the spacer dielectric material plate and with a respective sidewall of the phase change material plate.
    Type: Application
    Filed: March 18, 2024
    Publication date: March 20, 2025
    Inventors: Chang-Chih Huang, Yu-Wen Wang, Wei-Fang Chen, Han-Yu Chen, Kuo-Chyuan Tzeng
  • Patent number: 12256094
    Abstract: Video encoding or decoding methods and apparatuses include receiving input data associated with a current block in a current picture, determining a preload region in a reference picture shared by two or more coding configurations of affine prediction or motion compensation or by two or more affine refinement iterations, loading reference samples in the preload region, generating predictors for the current block, and encoding or decoding the current block according to the predictors. The predictors associated with the affine refinement iterations or coding configurations are generated based on some of the reference samples in the preload region.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: March 18, 2025
    Assignee: MEDIATEK INC.
    Inventors: Chih-Hsuan Lo, Tzu-Der Chuang, Ching-Yeh Chen, Chun-Chia Chen, Chih-Wei Hsu, Yu-Wen Huang
  • Publication number: 20250087650
    Abstract: A display panel includes a driving backplane, a light emitting component, a reflective structure and a bridging component. The driving backplane has a first pad and a second pad separated from each other. The light emitting component has a first electrode and a second electrode. The first electrode is electrically connected to the first pad of the driving backplane, and the first electrode is located between the second electrode and the first pad of the driving backplane. The reflective structure is disposed on the driving backplane and located at a periphery of the light emitting component. The bridging component is disposed on the light emitting component. One end of the bridging component is electrically connected to the second electrode. The bridging component passes across at least one portion of the reflective structure. The other end of the bridging component is electrically connected to the second pad of the driving backplane.
    Type: Application
    Filed: December 27, 2023
    Publication date: March 13, 2025
    Inventors: Yang-En WU, Chieh-Ming Chen, Bo-Ru Jian, Kuo-Hsuan Huang, Ta-Wen Liao, Yu-Chin Wu
  • Publication number: 20250080756
    Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, one or more model parameters of one or more cross-color models for the second-color block are determined. Then, cross-color predictors for the second-color block are determined, wherein one cross-color predictor value for the second-color block is generated for each second-color pixel of the second-color block by applying said one or more cross-color models to corresponding reconstructed or predicted first-color pixels. The input data associated with the second-color block is encoded using prediction data comprising the cross-color predictors for the second-color block at the encoder side, or the input data associated with the second-color block is decoded using the prediction data comprising the cross-color predictors for the second-color block at the decoder side.
    Type: Application
    Filed: December 20, 2022
    Publication date: March 6, 2025
    Inventors: Man-Shu CHIANG, Olena CHUBACH, Yu-Ling HSIAO, Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Patent number: 12242188
    Abstract: A photosensitive resin composition for imprinting, a cured article and an optical element are provided. The photosensitive resin composition for imprinting includes a resin (A), an ethylenically unsaturated monomer (B), a photoinitiator (C), a solvent (D), and a hydrophobic oligomer (E). The resin (A) has a weight average molecular weight of 1,000 to 50,000 and has two or more ethylenic polymerizable groups.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: March 4, 2025
    Assignee: eChem Solutions Corp.
    Inventors: Chin-Chen Huang, Yu-Lun Li, Chen-Wen Chiu
  • Publication number: 20250071260
    Abstract: A method and apparatus for video coding are disclosed. According to the method, a set of MC (Motion Compensation) candidates with each MC candidate comprising predicted samples for coding boundary pixels of the current block are determined. The set of MC candidates comprises a first candidate, and wherein the first candidate corresponds to a weighted sum of first predicted pixels generated according to first motion information of the current block and second predicted pixels generated according to second motion information of a neighbouring boundary block of the current block. Boundary matching costs associated with the set of MC candidates are determined respectively. A final candidate is determined from the set of MC candidates based on the boundary matching costs. The current block is encoded or decoded using the final candidate.
    Type: Application
    Filed: January 10, 2023
    Publication date: February 27, 2025
    Inventors: Chun-Chia CHEN, Olena CHUBACH, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20250071889
    Abstract: A flexible circuit board includes a flexible substrate, a chip, a first test area, first test pads and a circuit layer connected to the chip and the first test pads. A working area and a non-working area are defined on an upper surface of the flexible substrate. The chip is disposed on the working area, the first test area is located within the non-working area and between a third edge and the working area, the first test pads are arranged on the first test area. Flexible circuit boards with different sizes can have the first test area with the same size and can be tested using a probe card with the same specification to lower testing cost.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 27, 2025
    Inventors: Kung-Tzu Tu, Gwo-Shyan Sheu, Hsin-Hao Huang, Pei-Wen Wang, Yu-Chen Ma, Erh-Shun Chuang
  • Publication number: 20250063720
    Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yen-Chieh Huang, Wei-Gang Chiu, Kai-Wen Cheng, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20250063155
    Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, input data associated with a current block comprising at least one colour block are received. A blending predictor is determined according to a weighted sum of at least two candidate predictions generated based on one or more first hypotheses of prediction, one or more second hypotheses of prediction, or both. The first hypotheses of prediction are generated based on one or more intra prediction modes comprising a DC mode, a planar mode or at least one angular modes. The second hypotheses of prediction are generated based on one or more cross-component modes and a collocated block of said at least one colour block. The input data associated with the colour block is encoded or decoded using the blending predictor.
    Type: Application
    Filed: December 20, 2022
    Publication date: February 20, 2025
    Inventors: Man-Shu CHIANG, Olena CHUBACH, Chia-Ming TSAI, Yu-Ling HSIAO, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Patent number: 12230507
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
  • Publication number: 20250056823
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: D1063926
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: February 25, 2025
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Ning Chai, Yu-Wen Cheng, Tzu-Yung Huang, Wang-Hung Yeh
  • Patent number: D1063927
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: February 25, 2025
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Ning Chai, Yu-Wen Cheng, Tzu-Yung Huang, Wang-Hung Yeh