Patents by Inventor Yu-Wen Huang

Yu-Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240250030
    Abstract: An electronic device is provided. The electronic device includes an inductor and a dielectric layer. The inductor includes a first magnetic layer, a conductive trace over the first magnetic layer, and a second magnetic layer over the conductive trace. The dielectric layer includes a first portion between the second magnetic layer and an inclined surface of the first magnetic layer. A substantially constant distance between the second magnetic layer and the inclined surface of the first magnetic layer is defined by the dielectric layer.
    Type: Application
    Filed: January 23, 2023
    Publication date: July 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Chiu-Wen LEE, Yu-Hsun CHANG, Tai-Yuan HUANG
  • Publication number: 20240249991
    Abstract: A semiconductor structure includes a substrate having a front side and a back side, one or more dielectric layers over the front side, and a conductive structure. The one or more dielectric layers include a thermal sensor region and two dummy regions sandwiching the thermal sensor region along a second direction from a top view. The thermal sensor region and the two dummy regions extend longitudinally along a first direction generally perpendicular to the second direction from the top view. The conductive structure is embedded in the thermal sensor region of the one or more dielectric layers. The conductive structure includes conductive lines parallel to each other and extending longitudinally along the first direction, and conductive bars and vias electrically connecting the conductive lines. The conductive lines in a same dielectric layer of the one or more dielectric layers are electrically connected one by one zigzaggedly from the top view.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Inventors: Yu-Hsiang Chen, Hsiu-Wen Hsueh, Szu-Lin Liu, Wen-Sheh Huang, Chloe Hsin-Yi Chen, Wei-Lin Lai
  • Patent number: 12046506
    Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hsin Chan, Cai-Ling Wu, Chang-Wen Chen, Po-Hsiang Huang, Yu-Yu Chen, Kuan-Wei Huang, Jr-Hung Li, Jay Chiu, Ting-Kui Chang
  • Patent number: 12046510
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Patent number: 12038793
    Abstract: A hinge mechanism is provided, including a connecting unit, a hinge unit, and a locking element. The connecting unit has a connecting member and a tubular member. The tubular member is disposed on the connecting member. The hinge unit has a first member, a second member, a shaft, and a rod. The shaft pivotally connects the first member to the second member. The rod is affixed to the second member. The rod extends into the tubular member and has a slot. The locking element is fastened through the tubular member and joined in the slot.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: July 16, 2024
    Assignee: ACER INCORPORATED
    Inventors: Ting-Wen Pai, Yu-Shih Wang, Yi-Ta Huang, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
  • Patent number: 12040178
    Abstract: A semiconductor device structure and method for manufacturing the same are provided. The method includes forming a first resistive element over a substrate, and the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction. The method further includes forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element and forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction. In addition, the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiu-Wen Hsueh, Yu-Hsiang Chen, Wen-Sheh Huang, Chii-Ping Chen, Wan-Te Chen
  • Patent number: 12041248
    Abstract: A down-sample video coding system is provided. A decoding system receives to be decoded data from a bitstream for one or more pictures of a video. Each picture includes pixels having different color components. The decoding system receives up-down-sampling parameters that are applicable to a current video unit in the received data. The up-down-sampling parameters include different subsets for different color components. The decoding system decodes the data to reconstruct the current video unit. The decoding system up-samples the reconstructed current video unit according to the up-down-sampling parameters. The different color components of the current video unit are up-sampled according to different subsets of the up-down-sampling parameters.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: July 16, 2024
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Olena Chubach, Yu-Wen Huang, Ching-Yeh Chen
  • Patent number: 12040219
    Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Chung Huang, Chiung-Wen Hsu, Mei-Ju Kuo, Yu-Ting Weng, Yu-Chi Lin, Ting-Chung Wang, Chao-Cheng Chen
  • Publication number: 20240236329
    Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 11, 2024
    Inventors: Yu-Cheng LIN, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG, Yu-Wen HUANG
  • Patent number: 12021760
    Abstract: A routing establishing method for constructing a routing of a chain network including communication routers, each including a wired communication module, a wireless communication module, and a device configuration file. In a wired exploration procedure, exploration is performed by the source communication router through the wired communication module to obtain a wired communication status between the source and the destination communication routers. In a wireless exploration procedure, exploration is performed by the source communication router through the wireless communication module to obtain a wireless communication status between the source and the destination communication routers. In a routing decision procedure, next hop of the source communication router and whether the transmission routing is through the wired or the wireless communication module are determined and set according to the wired and the wireless communication status.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: June 25, 2024
    Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, CSBC CORPORATION, TAIWAN
    Inventor: Yu-Wen Huang
  • Patent number: 11997266
    Abstract: Methods and apparatus for loop-filter processing of reconstructed video are disclosed. According to one method, multiple CC-ALF (Cross-Component Adaptive Loop Filter) filters are used. Selection of the multiple CC-ALF filters can be signalled in one APS (Adaptation Parameter Set). According to another method, the CC-ALF can be implemented according to the difference between a to-be-process sample and its neighbouring sample.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: May 28, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Yu-Wen Huang, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Shaw-Min Lei
  • Patent number: 11991873
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
  • Patent number: 11985324
    Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11985314
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Patent number: 11979613
    Abstract: Encoding methods and apparatuses include receiving input video data of a current block in a current picture and applying a Cross-Component Adaptive Loop Filter (CCALF) processing on the current block based on cross-component filter coefficients to refine chroma components of the current block according to luma sample values. The method further includes signaling two Adaptive Loop Filter (ALF) signal flags and two CCALF signal flags in an Adaptation Parameter Set (APS) with an APS parameter type equal to ALF or parsing two ALF signal flags and two CCALF signal flags from an APS with an APS parameter type equal to ALF, signaling or parsing one or more Picture Header (PH) CCALF syntax elements or Slice Header (SH) CCALF syntax elements, wherein both ALF and CCALF signaling are present either in a PH or SH, and encoding or decoding the current block in the current picture.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: May 7, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Ching-Yeh Chen, Olena Chubach, Chen-Yen Lai, Tzu-Der Chuang, Chih-Wei Hsu, Yu-Wen Huang
  • Patent number: 11979593
    Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 7, 2024
    Assignee: MEDIATEK INC.
    Inventors: Shih-Chun Chiu, Tzu-Der Chuang, Ching-Yeh Chen, Chun-Chia Chen, Chih-Wei Hsu, Yu-Wen Huang
  • Patent number: 11973985
    Abstract: Various schemes pertaining to pre-encoding processing of a video stream with motion compensated temporal filtering (MCTF) are described. An apparatus determines a filtering interval for a received raw video stream having pictures in a temporal sequence. The apparatus selects from the pictures a plurality of target pictures based on the filtering interval, as well as a group of reference pictures for each target picture to perform pixel-based MCTF, which generates a corresponding filtered picture for each target picture. The apparatus subsequently transmits the filtered pictures as well as non-target pictures to an encoder for encoding the video stream. Subpictures of natural images and screen content images are separately processed by the apparatus.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 30, 2024
    Assignee: MediaTek Inc.
    Inventors: Chih-Yao Chiu, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Patent number: 11956421
    Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang