Patents by Inventor Yu-Wen Huang

Yu-Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230388546
    Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: Chih-Hsuan LO, Man-Shu CHIANG, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Patent number: 11832438
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Jared Stoeger, Yu-Wen Huang, Shu Zhou
  • Publication number: 20230369501
    Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Cheng Tan, Yu-Wen Huang, Hui-Min Chuang, Xiaojun Weng, Nikhil J. Mehta, Allen B. Gardiner, Shu Zhou, Timothy Jen, Abhishek Anil Sharma, Van H. Le, Travis W. Lajoie, Bernhard Sell
  • Publication number: 20230362403
    Abstract: Video encoding or decoding methods and apparatuses include receiving input data associated with a current block in a current picture, determining a preload region in a reference picture shared by two or more coding configurations of affine prediction or motion compensation or by two or more affine refinement iterations, loading reference samples in the preload region, generating predictors for the current block, and encoding or decoding the current block according to the predictors. The predictors associated with the affine refinement iterations or coding configurations are generated based on some of the reference samples in the preload region.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 9, 2023
    Inventors: Chih-Hsuan LO, Tzu-Der CHUANG, Ching-Yeh CHEN, Chun-Chia CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Patent number: 11805245
    Abstract: For each prediction candidate of a set of one or more prediction candidates of the current block, a video coder computes a matching cost between a set of reference pixels of the prediction candidate in a reference picture and a set of neighboring pixels of a current block in a current picture. The video coder identifies a subset of the reference pictures as major reference pictures based on a distribution of the prediction candidates among the reference pictures of the current picture. A bounding block is defined for each major reference picture, the bounding block encompassing at least portions of multiple sets of reference pixels for multiple prediction candidates. The video coder assigns an index to each prediction candidate based on the computed matching cost of the set of prediction candidates. A selection of a prediction candidate is signaled by using the assigned index of the selected prediction candidate.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: October 31, 2023
    Inventors: Chih-Yao Chiu, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20230345029
    Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Inventors: Shih-Chun CHIU, Tzu-Der CHUANG, Ching-Yeh CHEN, Chun-Chia CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Patent number: 11800102
    Abstract: Low-latency video coding methods and apparatuses include receiving input data associated with a current Intra slice composed of Coding Tree Units (CTU), where each CTU includes luma and chroma Coding Tree Blocks (CTBs), partitioning each CTB into non-overlapping pipeline units, and encoding or decoding the CTUs in the current Intra slices by performing processing of chroma pipeline units after beginning processing of luma pipeline units in at least one pipeline stage. Each of the pipeline units is processed by one pipeline stage after another pipeline stage, and different pipeline stages process different pipeline units simultaneously. The pipeline stage in the low-latency video coding methods and apparatuses simultaneously processes one luma pipeline unit and at least one previous chroma pipeline unit within one pipeline unit time interval.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 24, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Ming Tsai, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11792394
    Abstract: According to a method for Adaptive Loop Filter (ALF) processing of reconstructed video, multiple indicators are signaled in slice at an encoder side or parsed at a decoder side, where the multiple indicators are Adaptive Parameter Set (APS) indices associated with temporal ALF filter sets for the ALF processing. A current indicator is determined from the multiple indicators, where the current indicator is used to select a current ALF filter set. Filtered-reconstructed pixels are derived for the current block by applying the current ALF filter to the current block. In another method, if the ALF processing applied at a target sample requires an outside sample on other side of a target virtual boundary from the target sample, the outside sample is replaced by a padded sample.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: October 17, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20230328256
    Abstract: Methods and apparatus for video coding system utilizing Rate-Distortion Optimized Quantization (RDOQ) are provided. According to one method, a rate for a level belonging to a level set of a current quantized transform coefficient is estimated for a current coefficient group (CG) based on neighboring quantized coefficients of the current quantized transform coefficient and the current CG. A best level for the current quantized transform coefficient is selected from the level set for a best RD-cost. In another method, a TB is partitioned into M regions and M best regions are derived for the M regions according to RDOQ. At least two alternative region RD-costs are generated for each of the M best regions based on a relative position between each of the M best regions and a last significant region in the TB. TB RD-cost for the TB is selected according a last non-zero best region position.
    Type: Application
    Filed: April 6, 2022
    Publication date: October 12, 2023
    Inventors: Chen-Yen LAI, Tzu-Der CHUANG, Ching-Yeh CHEN, Chun-Chia CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Patent number: 11785204
    Abstract: Various schemes for realizing JCCR mode decision in frequency domain are described. An apparatus receives first and second pixel data of a current block of a picture and transform the pixel data into first and second transformed data in frequency domain. The apparatus generates joint pixel data comprising a pixelwise linear combination of the first and second transformed data. The apparatus generates reconstructed joint pixel data based on the joint pixel data by quantization and inverse quantization operations. The apparatus derives first and second reconstructed pixel data based on the reconstructed joint pixel data. The apparatus accordingly calculates first and second distortion values in frequency domain, based on which a preferred mode may be determined to code the current block.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: October 10, 2023
    Inventors: Chen-Yen Lai, Tzu-Der Chuang, Ching-Yeh Chen, Chih-Wei Hsu, Chun-Chia Chen, Yu-Wen Huang
  • Patent number: 11778235
    Abstract: A method for performing transform skip mode (TSM) in a video decoder is provided. A video decoder receives data from a bitstream to be decoded as a plurality of video pictures. The video decoder parses the bitstream for a first syntax element in a sequence parameter set (SPS) of a current sequence of video pictures. When the first syntax element indicates that transform skip mode is allowed for the current sequence of video pictures and when transform skip mode is used for a current block in a current picture of the current sequence, the video decoder reconstructs the current block by using quantized residual signals that are not transformed.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: October 3, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Shih-Ta Hsiang, Lulin Chen, Tzu-Der Chuang, Chih-Wei Hsu, Ching-Yeh Chen, Olena Chubach, Yu-Wen Huang
  • Publication number: 20230300370
    Abstract: Method and apparatus of Inter prediction for video coding are disclosed. When a sub-block motion compensation coding tool is selected for the current block, the method generates sub-block MVs (motion vectors) associated with multiple sub-blocks, which are included or contained in the current block, according to the sub-block motion compensation coding tool, constrains the sub-block MVs within a range to form constrained sub-block MVs, and applies motion compensation to the current block using the constrained sub-block MVs or applies motion compensation to the current block using one sub-block MV within the range around the primary MV in a second list if a corresponding sub-block MV in a first list is outside the range. In another method, motion compensation is applied to the current block only using reference pixels of reference sub-blocks within a primary reference block.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 21, 2023
    Applicant: HFI INNOVATION INC.
    Inventors: Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG, Chih-Wei HSU
  • Patent number: 11765365
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream determines a block boundary of the current block and sub-block boundaries inside the current block, wherein the current block is partitioned into a plurality of sub-blocks using sub-block mode prediction. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a current filtered-reconstructed block, wherein said applying the de-blocking process to the current block comprises applying the de-blocking process to the sub-block boundaries inside the current filtered-reconstructed block, and generates a filtered decoded picture including the current filtered-reconstructed block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: September 19, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11765384
    Abstract: Methods and apparatus of motion compensation using the bi-directional optical flow (BIO) techniques are disclosed. According to one method of the present invention, the BIO process is applied to encode or decode bi-directional current block in Merge mode only or in AMVP (advanced motion vector prediction) mode only. According to another method, the BIO process conditionally to encode or decode the current block depending on a jointly-coded flag if the current block is coded using a bi-prediction mode. According to yet another method, x-offset value vx and y-offset value vy for the current block are added to the current motion vector to form a final motion vector. The final motion vector is then used as a reference motion vector for following blocks. In still yet another method, the BIO process is applied to the chroma component.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: September 19, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20230290722
    Abstract: An integrated circuit (IC) includes a first memory cell and a second memory cell. The first memory cell includes (i) a first transistor and (ii) a first capacitor coupled to the first transistor, where an upper electrode of the first capacitor is coupled to a first conductive structure. The second memory cell is above the first memory cell. The second memory cell includes (i) a second transistor and (ii) a second capacitor coupled to the second transistor. An upper electrode of the second capacitor is coupled to a second conductive structure. In an example, an interconnect feature includes a continuous and monolithic body of conductive material. In an example, the continuous and monolithic body extends through the second conductive structure, and further extends through the first conductive structure. In an example, the first and second memory cells are dynamic random access memory (DRAM) memory cells.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Applicant: Intel Corporation
    Inventors: Travis W. Lajoie, Juan Alzate Vinasco, Abhishek Anil Sharma, Van H. Le, Moshe Dolejsi, Yu-Wen Huang, Kimberly Pierce, Jared Stoeger, Shem Ogadhoh
  • Patent number: 11743458
    Abstract: Methods and apparatus for in-loop processing of reconstructed video are disclosed. According to one method, a virtual boundary is determined for to-be-processed pixels in the current picture, where the virtual boundary is aligned with block boundaries and at least one to-be-processed pixel on a first side of the virtual boundary requires one or more second pixels on a second side of the virtual boundary. According to the method, the in-loop processing is modified if a target to-be-processed pixel requires at least one second pixel from the second side of the virtual boundary and the modified in-loop processing eliminates the need for any second pixel on the second side of the virtual boundary. According to another method, the operations of block classification are changed when part of the required pixels in one 10×10 window used in classification are at the other side of virtual boundaries.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: August 29, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Ching-Yeh Chen, Tzu-Der Chuang, Yu-Chi Su, Chih-Wei Hsu, Yu-Wen Huang
  • Patent number: 11736704
    Abstract: Video encoding methods and apparatuses for Sum of Absolute Transformed Difference (SATD) computation by folded Hadamard transform circuits include splitting a current block into SATD blocks, receiving input data associated with a first block of a first SATD block in a first cycle and receiving input data associated with a second block of the first SATD block in a second cycle, and performing calculations for the first block by shared Hadamard transform circuits in the first cycle and performing calculations for the second block by the shared Hadamard transform circuits in the second cycle. Each shared Hadamard transform circuit is a first part of each folded Hadamard transform circuit. The video encoding methods and apparatuses further perform calculations for the entire SATD block by a final part of each folded Hadamard transform circuit to generate a final SATD result of the first SATD block for encoding.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: August 22, 2023
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Yen Chuang, Man-Shu Chiang, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20230224455
    Abstract: A method and apparatus for video coding. According to the method, a set of candidates associated with coding modes or mode parameters are determined. Boundary matching costs associated with the set of candidates are determined, where each of the boundary matching costs is determined for one target candidate of the set of candidates. The costs are calculated by using reconstructed or predicted samples of the current block and one or more neighboring blocks of the current block. Each of the boundary matching costs is calculated using one target configuration selected from a plurality of configurations. A final candidate is selected from the set of candidates based on the boundary matching costs. The current block is encoded or decoded using the final candidate.
    Type: Application
    Filed: December 13, 2022
    Publication date: July 13, 2023
    Inventors: Man-Shu CHIANG, Chun-Chia CHEN, Chih-Wei HSU, Shih-Ta HSIANG, Ching-Yeh CHEN, Tzu-Der CHUANG, Yu-Wen HUANG
  • Patent number: 11700391
    Abstract: Method and apparatus of Inter prediction for video coding are disclosed. When a sub-block motion compensation coding tool is selected for the current block, the method generates sub-block MVs (motion vectors) associated with multiple sub-blocks, which are included or contained in the current block, according to the sub-block motion compensation coding tool, constrains the sub-block MVs within a range to form constrained sub-block MVs, and applies motion compensation to the current block using the constrained sub-block MVs or applies motion compensation to the current block using one sub-block MV within the range around the primary MV in a second list if a corresponding sub-block MV in a first list is outside the range. In another method, motion compensation is applied to the current block only using reference pixels of reference sub-blocks within a primary reference block.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 11, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Chih-Wei Hsu
  • Publication number: 20230199170
    Abstract: A video coding system generating candidates for Merge Mode with Motion Vector Difference (MMVD) with reduced resource usage is provided. The system receives data to be encoded or decoded as a current block of a current picture of a video. The system identifies multiple MMVD candidates for different offset positions based on a merge candidate of the current block. The system generates reference samples for the identified MMVD candidates. The system reconstructs the current block or encodes the current block into a bitstream by using the generated reference samples. The system processes the MMVD candidates in separate groups: a first group of vertical MMVD candidates and a second group of horizontal MMVD candidates. The system generates the reference samples for the identified MMVD candidates by applying a vertical filter to source reference samples of horizontal MMVD candidates and then applying a horizontal filter to outputs of the vertical filter.
    Type: Application
    Filed: October 31, 2022
    Publication date: June 22, 2023
    Inventors: Cheng-Yen Chuang, Man-Shu Chiang, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang