Patents by Inventor Yu Yang

Yu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087989
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Josh LIN, Chung-Jen HUANG, Yun-Chi WU, Tsung-Yu YANG
  • Publication number: 20240088463
    Abstract: A system, method, and computer program product for determining the cause of a battery condition, such as a thermal runaway event, are provided. An example battery safety evaluation system may include a battery having a housing and an interior battery compartment. The battery safety evaluation system may include internal sensing elements attached to the interior battery compartment and configured to capture data representative of an internal battery condition event. The battery safety evaluation system may further include an external sensing element attached to the battery housing and configured to capture data representative of an external battery condition event. In addition, the battery safety evaluation system may include a controller for determining a cause of the battery condition based at least in part on a time sequence of events generated from the internal data captured by the internal sensing element and the external data captured by the external sensing element.
    Type: Application
    Filed: August 21, 2023
    Publication date: March 14, 2024
    Inventors: Fan YANG, Wu CHEN, Yu HU, Jie WANG
  • Publication number: 20240089070
    Abstract: A method for determining beam application time includes: receiving, by a terminal, beam indication signaling, where the beam indication signaling is used to indicate common beam information; determining, by the terminal, a target subcarrier spacing according to a subcarrier spacing determining rule, where the target subcarrier spacing includes a first target subcarrier spacing corresponding to N component carriers CCs or a second target subcarrier spacing corresponding to a first bandwidth part BWP of the N CCs, the first BWP is a BWP to which the common beam information is applied; and determining, by the terminal, a beam application time based on the target subcarrier spacing, where the beam application time includes a first beam application time corresponding to the N CCs or a second beam application time corresponding to the first BWP of the N CCs.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Yu YANG, Peng SUN
  • Publication number: 20240087932
    Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung TSAI, Ping-Cheng KO, Fang-yu LIU, Jhih-Yuan YANG
  • Publication number: 20240084256
    Abstract: The present invention pertains to a method for culturing cord blood-derived natural killer cells using transformed T-cells. The method for culturing natural killer cells using transformed T-cells according to the present invention can effectively propagate and produce natural killer cells from a small amount of raw cells. In addition, the method can also improve the cell-killing ability of natural killer cells. Thus, the method for culturing natural killer cells using transformed T-cells according to the present invention can be usefully used to commercialize cell therapeutic agents. Moreover, natural killer cells produced by the culturing method of the present invention can be usefully used as a cell therapeutic agent.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 14, 2024
    Inventors: YUSUN KIM, EUN JI KIM, GYEONG-MIN PARK, BITNA YANG, BOKYUNG MIN, SUNGYOO CHO, YU KYEONG HWANG
  • Publication number: 20240088125
    Abstract: Devices and methods of manufacture for a deep trench layout area-saving semiconductor structure for use with bipolar-CMOS-DMOS (BCD) devices. A semiconductor device may comprise a first BCD device formed within a first perimeter of a first BCD layout area, and a deep trench isolation structure defining the first perimeter of the first BCD layout area, in which the deep trench isolation structure may comprise a first rounded corner that may define a first corner of the first BCD layout area. A semiconductor device may comprise, a substrate, BCD device formed on the substrate, and a deep trench isolation structure laterally surrounding the BCD device. The deep trench isolation structure, with respect to a top-down view, may comprise vertical portions, horizontal portions, a “T”-shaped intersection connecting at least one vertical portion and at least one horizontal portion, and a cross-shaped intersection connecting two vertical portions and two horizontal portions.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Tsung-Yu YANG, Po-Wei LIU
  • Publication number: 20240088291
    Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chang Sun, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, TsuChing Yang, Feng-Cheng Yang, Chung-Te Lin
  • Patent number: 11929418
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Patent number: 11926538
    Abstract: The present disclosure relates to the technical field of wastewater treatment, and provides a wastewater treatment method and apparatus based on hydrate-based water vapor adsorption. The apparatus includes a wastewater evaporation zone, a hydrate formation zone, a hydrate decomposition zone, and a data acquisition and control system. Rising water vapor and condensed water formed during evaporation of wastewater at normal temperature react with a hydrate former on a cooling wall surface to form a hydrate, continuous evaporation of the wastewater is promoted, the hydrate is scraped off to a collecting zone below by a scraper after being formed, and the hydrate is decomposed into fresh water, thereby realizing wastewater treatment. The present disclosure provides a method for treating complex wastewater containing a plurality of pollutants, where water vapor is consumed to form the hydrate to promote wastewater evaporation, and water obtained from the decomposition does not contain pollutants theoretically.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: March 12, 2024
    Assignee: DALIAN UNIVERSITY OF TECHNOLOGY
    Inventors: Yongchen Song, Lunxiang Zhang, Huilian Sun, Zheng Ling, Jiafei Zhao, Lingjie Sun, Lei Yang, Mingjun Yang, Yu Liu, Weiguo Liu, Yanghui Li, Xiang Sun, Lanlan Jiang
  • Patent number: 11929331
    Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 11926922
    Abstract: The embodiments of the present disclosure disclose a method and an apparatus for crystal growth. The method for crystal growth may include: placing a seed crystal and a target source material in a growth chamber of an apparatus for crystal growth; executing a growth of a crystal based on the seed crystal and the target source material according to physical vapor transport; determining whether a preset condition is satisfied during the crystal growth process; and in response to determining that the preset condition is satisfied, replacing a sublimated target source material with a candidate source material. In the present disclosure, by replacing the sublimated target source material with the candidate source material, a crystal with large-size and high-quality can be grown.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 12, 2024
    Assignee: MEISHAN BOYA ADVANCED MATERIALS CO., LTD.
    Inventors: Yu Wang, Tian Yang, Zhenxing Liang, Min Li
  • Patent number: 11930715
    Abstract: A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 11927077
    Abstract: A high-frequency composite impactor including a high-frequency axial and a torsional impact assembly is disclosed. The high-frequency axial impact assembly includes an upper self-excited oscillation cavity, a lower self-excited oscillation cavity, an adjustment block and a lock nut. The torsional impact assembly includes an upper end cover, a reversing switch, a pendulum, a lower shell, a lower end cover, a nozzle, a connecting block and a retaining ring. The high-frequency axial impact assembly converts the flowing drilling fluid into a pulsed jet to achieve a high-frequency axial impact. The torsional impact assembly enables a torsional impact through a shunt, and finally enables a high-frequency composite impact, which can effectively reduce the stick-slip of the drill string, jump drilling and other downhole accidents. By reducing the friction between the drill string and the borehole wall, the impactor can reduce WOB loss, increase the ROP, and improve the drilling efficiency.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 12, 2024
    Assignees: Southwest Petroleum University, Sichuan Xieming Technology Co., Ltd.
    Inventors: Jialin Tian, Lanhui Mao, Yanniu Ren, Lin Yang, Haolin Song, Bo He, Jun Li, Lei Cha, Zhe Zhang, Yu Wei
  • Patent number: 11930199
    Abstract: A method of decoding a bitstream by an electronic device is provided. The method determines a block unit from an image frame received from the bitstream. To reconstruct the block unit, the method receives, from a candidate list, first motion information having a first list flag for selecting a first reference frame and second motion information having a second list flag for selecting a second reference frame. The method then stores a predefined one of the first and second motion information for a sub-block determined in the block unit when the first list flag is identical to the second list flag.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 12, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Chih-Yu Teng, Yu-Chiao Yang, Po-Han Lin
  • Publication number: 20240081157
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240080692
    Abstract: Methods, systems, and devices for wireless communications are described. In some wireless communications systems, a user equipment (UE) and a network entity may utilize multi-port mobility reference signals to assist with spatial based mobility procedures. The UE may receive a reference signal that is associated with multiple antenna ports. The UE may measure a multi-dimensional channel response based on the reference signal. The multi-dimensional channel response may be associated with measured channel metrics corresponding to the multiple antenna ports. The UE may transmit a report that includes a channel measurement vector based on the multi-dimensional channel response. The channel measurement vector may indicate multiple measured channel metrics for one or more dimensions of the multi-dimensional channel response. The network entity may transmit a message that indicates one or more metrics associated with mobility management for the UE based on the report that indicates the channel measurement vector.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Jing Jiang, Jae Won Yoo, Yongle Wu, Lei Xiao, Hari Sankar, Alexei Yurievitch Gorokhov, Yu Zhang, Wei Yang, Jing Lei
  • Publication number: 20240081103
    Abstract: A display substrate and a display device are disclosed. In the display substrate, a plurality of openings include a plurality of opening groups, the plurality of opening groups include a plurality of opening group rows, each of the opening groups includes a first opening and a second opening, the plurality of opening group rows includes a first opening group row and a second opening group row, the spacer is located between the first opening of the first opening group row and the second opening of the second opening group row, an orthographic projection of the first opening includes a first long edge, and an orthographic projection of the second opening includes a second long edge, the first long edge is parallel to the second long edge, an extension line of the first long edge is misaligned from an extension line of the second long edge.
    Type: Application
    Filed: October 11, 2023
    Publication date: March 7, 2024
    Inventors: Hao ZHANG, Tingliang LIU, Yu WANG, Huijun LI, Huijuan YANG, Xiaofeng JIANG, Xin ZHANG, Jie DAI, Lu BAI, Pengfei YU, Tinghua SHANG
  • Publication number: 20240080148
    Abstract: A CSI measurement resource processing method and apparatus, a terminal, and a readable storage medium. The CSI measurement resource processing method in embodiments of this application includes: performing, by a terminal, a first processing operation on a first measurement resource based on configuration information configured by a network-side device; and reporting, by the terminal, a processing result of the first processing operation, where the first measurement resource includes one or multiple CSI measurement resources, the configuration information includes an association relationship between the CSI measurement resources and multiple transmission and reception points TRPs or cells, and the first processing operation includes at least one of the following: channel measurement and interference measurement.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Applicant: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Chenxi WANG, Peng SUN, Yu YANG, Rakesh TAMRAKAR, Yang SONG
  • Patent number: 11924131
    Abstract: Embodiments of the present invention disclose a beam indication method and apparatus, a device, and a medium. The method includes: receiving beam indication information transmitted by a network-side device, where the beam indication information is used to indicate a plurality of pieces of beam information of a channel or a reference signal, and the plurality of pieces of beam information correspond to different transmission and reception point TRP identification information; and transmitting the channel or the reference signal according to the beam indication information.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventor: Yu Yang
  • Patent number: 11922838
    Abstract: A display panel, comprising a first insulating structural layer, a first crack detection line, a second insulating structural layer and a second crack detection line which are sequentially arranged on a substrate, wherein the first crack detection line and the second crack detection line are both located in a peripheral area and are arranged around a display area, one end of the first crack detection line is configured to receive a detection signal, and the other end of the first crack detection line is configured to output a first output signal, and one end of the second crack detection line is configured to receive a detection signal and the other end of the second crack detection line is configured to output a second output signal.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: March 5, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yu Wang, Yi Zhang, Tingliang Liu, Chang Luo, Hao Zhang, Huijuan Yang, Tinghua Shang, Yang Zhou, Pengfei Yu, Shun Zhang, Xiaofeng Jiang, Huijun Li, Linhong Han