Patents by Inventor Yu Yang

Yu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250150038
    Abstract: A noise elimination device for a Class-D audio amplifier includes a residual signal detector and a multiplexer, wherein the multiplexer is electrically connected with a sigma-delta modulator (SDM) and a pulse width modulator (PWM) of the Class-D audio amplifier and the residual signal detector. The residual signal detector is configured to detect whether an input signal of the Class-D audio amplifier is residual. The multiplexer is configured to output zero data into the pulse width modulator when the residual signal detector detects that the input signal of the Class-D audio amplifier is residual.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Inventors: Hsin-Yuan Chiu, Hsiang-Yu Yang, Tien-I Yang
  • Publication number: 20250150495
    Abstract: A method for handling a call using Sessions Initiation Protocol (SIP) includes sending an INVITE or a first media type by a network side to user equipment, sending an UPDATE of a second media type by the user equipment to the network side, receiving an SIP global failure response for the UPDATE by the user equipment from the network side, sending an SIP success response for the INVITE of the first media type by the user equipment to the network side, receiving an ACK of the first media type by the user equipment from the network side, and establishing a call session of the first media type between the user equipment and the network side.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 8, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ying-Cen Lai, Chien-Yi Wang, Nuan-Yu Yang
  • Publication number: 20250150847
    Abstract: A channel information determining method, and a non-transitory computer-readable storage medium are provided. The method includes: updating, activating, or indicating parameter information of a first channel or a first reference signal RS by using a media access control MAC control element CE command, where the parameter information of the first channel or the first reference signal RS is used for determining the parameter information of a second channel or a second RS under a preset condition; and the parameter information includes spatial relation information.
    Type: Application
    Filed: December 27, 2024
    Publication date: May 8, 2025
    Applicant: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Yu YANG, Peng SUN
  • Patent number: 12294433
    Abstract: A signal to interference plus noise ratio measurement method, a terminal device, and a medium are provided. The signal to interference plus noise ratio measurement method includes receiving configuration information from a network side device. The signal to interference plus noise ratio measurement method further includes performing Signal to Interference plus Noise Ratio (SINR) measurement by using information that is of a Reference Signal (RS) resource used for a SINR measurement and that is included in the configuration information, where a number of measurement times of the RS resource in the SINR measurement meets a preset rule.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: May 6, 2025
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Yu Yang, Peng Sun
  • Patent number: 12294026
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a gate dielectric layer on the barrier layer; forming a work function metal layer on the gate dielectric layer; patterning the work function metal layer and the gate dielectric layer; forming a gate electrode on the work function metal layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
    Type: Grant
    Filed: December 18, 2023
    Date of Patent: May 6, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 12293221
    Abstract: Methods, systems, and computer-readable storage media for receiving, by a cross-process scheduling engine executed within a cloud platform, work scenario metadata and sensitivity metadata, generating, by the cross-process scheduling engine, a lineage graph representing relationships between one or more of data and processes to be executed for a work scenario represented by the work scenario metadata, defining, by the cross-process scheduling engine, a set of tile segments for the work scenario based on the lineage graph and the sensitivity metadata, dispatching, by the cross-process scheduling engine, a first sub-set of tile segments for execution in a private deployment including one or more private nodes, and dispatching, by the cross-process scheduling engine, a second sub-set of tile segments for execution in a public deployment including one or more public nodes.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: May 6, 2025
    Assignee: SAP SE
    Inventors: Le Zhang, Daping Wang, Haoxing Hou, Moritz Semler, Yu Yang
  • Patent number: 12284123
    Abstract: A method for indicating antenna panel information of a terminal, a network side device, and a terminal are provided. The indication method applied to a network side device includes: sending configuration information of a first SRS resource set to a terminal, where the configuration information includes an identifier of the first SRS resource set, and the identifier of the first SRS resource set is used to indicate an identifier of an antenna panel of the terminal.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 22, 2025
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Yu Yang, Peng Sun
  • Patent number: 12282406
    Abstract: A first device generates a first capability model instance based on a capability model template, and sends the first capability model instance to a network management device. The capability model template includes one or more metric names. The first capability model instance includes one or more performance parameters that can be subscribed to by the first device, and the one or more performance parameters are parameters corresponding to one or more metric names. The first capability model instance is used by the network management device to select and subscribe to one or more performance parameters from the one or more performance parameters that can be subscribed to by the first device.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: April 22, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zitao Wang, Qin Wu, Bo Wu, Xiaopeng Qin, Yu Yang
  • Publication number: 20250126210
    Abstract: A voice call management method is provided. The voice call management method may be applied to an apparatus. The voice call management method may include the following steps. The apparatus may determine the current scenario associated with the operation environment of the apparatus. Then, the apparatus may determine to perform a voice call through a modem (MD) voice engine or through an application processor (AP) voice engine according to the current scenario.
    Type: Application
    Filed: October 9, 2024
    Publication date: April 17, 2025
    Inventors: Hao-Cheng WANG, Kuan-Ming LIN, Nuan-Yu YANG, Chien-Yi WANG
  • Patent number: 12279446
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.
    Type: Grant
    Filed: April 24, 2024
    Date of Patent: April 15, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Ruei-Jhe Tsao, Che-Hua Chang
  • Patent number: 12279064
    Abstract: An image compensation circuit for controlling a luminance of a display panel is configured to: receive a plurality of image data; perform gamma tuning to convert the plurality of image data into a plurality of original gamma codes according to a plurality of first compensation values corresponding to a first operation mode; calculate a plurality of gamma difference values between the plurality of first compensation values and a plurality of second compensation values corresponding to a second operation mode; and calculate a plurality of output gamma codes corresponding to the second operation mode according to the plurality of original gamma codes by using the plurality of gamma difference values.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: April 15, 2025
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Wei-Jhe Ma, Feng-Ting Pai, Jun-Yu Yang, Hsin-Yu Pan
  • Publication number: 20250114474
    Abstract: Provided are a composition and a method for preventing thrombogenesis. The composition includes a conjugate of heparin and a viral capsid protein, wherein the heparin is covalently bonded with the viral capsid protein.
    Type: Application
    Filed: October 7, 2024
    Publication date: April 10, 2025
    Inventors: Chia-Ching CHANG, Chia-Yu CHANG, Chih-Yu YANG
  • Patent number: 12274080
    Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, forming a channel layer, a barrier layer, and a first passivation layer sequentially on the substrate, forming a plurality of trenches through at least a portion of the first passivation layer, forming a second passivation layer on the first passivation layer and covering along sidewalls and bottom surfaces of the trenches, and forming a conductive plate structure on the second passivation layer and filling the trenches.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: April 8, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Yu Yang, Hsun-Wen Wang
  • Patent number: 12266722
    Abstract: The present disclosure relates to a semiconductor device and its manufacturing method, and the semiconductor device includes a substrate, a channel layer, a gate electrode, a first electrode, a second electrode, and a metal plate. The channel layer is disposed on the substrate, and the gate electrode is disposed on the channel layer. The first electrode and the second electrode are disposed on the channel layer, at two opposite sides of the gate electrode respectively. The metal plate is disposed over the channel layer, between the first electrode and the gate electrode. The metal plate includes a first extending portion and a second extending portion, wherein the second extending portion extends towards the substrate without contacting the channel layer, and the first extending portion extends toward and directly contacts the first electrode or the second electrode.
    Type: Grant
    Filed: March 21, 2021
    Date of Patent: April 1, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Yu Yang, Hsun-Wen Wang
  • Patent number: 12267594
    Abstract: An image compensation circuit for an image sensor includes a gain amplifier, a compensation control circuit, a memory and a digital-to-analog converter (DAC). The gain amplifier is used for receiving a plurality of image signals from the image sensor and amplifying the plurality of image signals. The compensation control circuit is used for generating a plurality of compensation values for the plurality of image signals. The memory, coupled to the compensation control circuit, is used for storing the plurality of compensation values. The DAC, coupled to the memory and the gain amplifier, is used for converting the plurality of compensation values into a plurality of compensation voltages, respectively, to compensate the plurality of image signals with the plurality of compensation voltages.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: April 1, 2025
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Jung-Yu Tsai, Chen-Tsung Wu, Kuan-Lin Wu, Hung-Yu Yang
  • Patent number: 12267041
    Abstract: A power electronic device on a direct-current side of a photovoltaic system, and a test system and a control method therefor, achieving a simple, fast, and low-cost functional test on the power electronic device during a production process or a troubleshooting process of the power electronic device on the direct-current side of the photovoltaic system. The power electronic device is used for detecting a fluctuation of an electric signal parameter of an input end of the power electronic device; when the fluctuation meets a preset condition, the device is switched from a limited output state to a non-limited output state; the fluctuation of the electric signal parameter of the input end is generated by applying a disturbance to the input end of the power electronic device on the direct-current side of the photovoltaic system by a direct-current power supply having a disturbance output.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 1, 2025
    Assignee: Sungrow Power Supply Co., Ltd.
    Inventors: Yu Yang, Qiaodi Chen, Yuqi Peng, Jun Xu
  • Patent number: 12266577
    Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Ling Shih, Tsung-Yu Yang, Yun-Chi Wu, Po-Wei Liu
  • Patent number: 12268028
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. A semiconductor channel layer is formed on the substrate. A semiconductor barrier layer is formed on the semiconductor channel layer. An etching process is performed to expose a portion of the semiconductor channel layer. A dielectric layer is formed to cover the semiconductor barrier layer and the exposed semiconductor channel layer. A first electrode is formed after forming the dielectric layer, where the first electrode includes a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.
    Type: Grant
    Filed: December 24, 2023
    Date of Patent: April 1, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Publication number: 20250099431
    Abstract: The present disclosure provides GLP-1R agonists, and compositions, methods, and kits thereof. Such compounds are generally useful for treating a GLP-1R mediated disease or condition.
    Type: Application
    Filed: September 19, 2024
    Publication date: March 27, 2025
    Inventors: Stephen E. Ammann, Gediminas J. Brizgys, James S. Cassidy, Elbert Chin, Chienhung Chou, Jeromy J. Cottell, Chao-I Hung, Kavoos Kolahdouzan, Daniel G. Shore, Suzanne M. Szewczyk, James G. Taylor, Rhiannon Thomas-Tran, Nathan E. Wright, Zheng-yu Yang
  • Publication number: 20250105099
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Josh LIN, Chung-Jen HUANG, Yun-Chi WU, Tsung-Yu YANG