Patents by Inventor Yu Yang

Yu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949886
    Abstract: Methods for determining a prediction value, an encoder, and a decoder are provided. Reconstructed values of neighboring samples of a current block are acquired, and then filtered to obtain a reference value set of the current block. When a size of the current block is smaller than a preset threshold value, a first constant value is calculated according to a bit depth value of a luma component of a sample in the current block. A difference between the first constant value and a first reference value in the reference value set is determined as a first prediction input value in a prediction input value set. Other prediction input values in the prediction input value set other than the first prediction input value are determined according to the reference value set. Prediction values of samples at specific positions in the current block is calculated and then filtered.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: April 2, 2024
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Junyan Huo, Yanzhuo Ma, Shuai Wan, Fuzheng Yang, Wei Zhang, Haixin Wang, Yu Sun
  • Patent number: 11945076
    Abstract: An article (100) has a polyester film backing (110) and a primer layer (120) including a carboxylated styrene butadiene copolymer crosslinked with a polyfunctional aziridine disposed on a major surface of the polyester film backing (110). Another article includes a polyester backing (110), a primer layer (120) including a carboxylated styrene butadiene copolymer crosslinked with a polyfunctional aziridine disposed on a major surface of the polyester backing (110), and a phenolic layer (140) disposed on the primer layer (120) on a surface opposite the polyester backing (110). The phenolic layer (120) can include abrasive particles (160). Processes for making the articles are also described, as well as methods for abrading a workpiece and improving adhesion between a polyester film backing (110) and a phenolic layer (120) on the polyester backing (110).
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: April 2, 2024
    Assignee: 3M Innovative Properties Company
    Inventors: Amelia W. Koenig, Liming Song, Stephen M. Sanocki, Yu Yang, Yaohua Gao, Aniruddha A. Upadhye, Morgan A. Priolo, Saurabh Batra, Angela S. McLean
  • Patent number: 11950102
    Abstract: Embodiments of the present disclosure provide a method for beam management in an unlicensed band, a terminal device, and a network device. The method includes: receiving, by a terminal device, a reference signal resource from a network device; measuring, by the terminal device, the reference signal resource in the unlicensed band, to obtain a beam measurement result; and sending, by the terminal device using an uplink resource for transmitting a beam report, the beam report comprising the beam measurement result.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: April 2, 2024
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventor: Yu Yang
  • Patent number: 11950245
    Abstract: A method and a device for cross carrier scheduling a physical downlink shared channel are provided. The method includes: receiving downlink control information DCI, where the DCI is used to indicate cross carrier scheduling a physical downlink shared channel PDSCH; determining target quasi-colocation QCL information of the cross carrier scheduled PDSCH; and receiving the cross carrier scheduled PDSCH based on the target QCL information.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: April 2, 2024
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Yu Yang, Peng Sun
  • Patent number: 11948281
    Abstract: Methods and systems are provided for accurately filling holes, regions, and/or portions of high-resolution images using guided upsampling during image inpainting. For instance, an image inpainting system can apply guided upsampling to an inpainted image result to enable generation of a high-resolution inpainting result from a lower-resolution image that has undergone inpainting. To allow for guided upsampling during image inpainting, one or more neural networks can be used. For instance, a low-resolution result neural network (e.g., comprised of an encoder and a decoder) and a high-resolution input neural network (e.g., comprised of an encoder and a decoder). The image inpainting system can use such networks to generate a high-resolution inpainting image result that fills the hole, region, and/or portion of the image.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: April 2, 2024
    Assignee: Adobe Inc.
    Inventors: Zhe Lin, Yu Zeng, Jimei Yang, Jianming Zhang, Elya Shechtman
  • Patent number: 11948990
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11944867
    Abstract: A new kind of portable hangboard intended for finger strength exercises allows the user to adjust the angle of the hangboard and the depth of the finger slot to control the difficulty of the exercise. The main body of the hangboard hangs on a rope. The main body of the hangboard contains multiple slots that the rope can pass through to adjust the angle of the device. The finger slot contained in the main body has magnets at the deep end which allow one or more shims with built in magnets to be inserted to make the slot shallower. The hangboard offers greater portability and variety of exercises compared to other inventions of this class.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: April 2, 2024
    Inventors: Taras Karpachevskyy, Li Yu Yang
  • Patent number: 11947211
    Abstract: A display panel includes: a liquid crystal cell; an optical layer configured to transmit part of light incident onto the optical layer whose polarization direction is parallel to a transmission axis of the optical layer, and reflect a remaining part of the light incident onto the optical layer; a first polarization structure configured to transmit part of light incident onto the first polarization structure whose polarization direction is parallel to a transmission axis of the first polarization structure, and absorb a remaining part of the light incident onto the first polarization structure; and a second polarization structure configured to transmit part of light incident onto the second polarization structure whose polarization direction is parallel to a transmission axis of the second polarization structure, and absorb a remaining part of the light incident onto the second polarization structure.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 2, 2024
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jing Wang, Yangyang Cai, Guojian Qu, Guangyun Tong, Fan Yang, Chengwei Wang, Zhanchang Bu, Bochang Wang, Yu Zhang, Hetao Wang, Xiang Li
  • Publication number: 20240105401
    Abstract: A keyswitch structure includes a casing, a first support, a second support, and a pressing stem. The casing forms an accommodating space and an opening communicating with the accommodating space. The first and second supports are disposed in the accommodating space and are directly and rotatably connected with the casing; the supports are also pivotally connected with each other. The pressing stem extends into the accommodating space to be rotatably connected with the first and second supports and protrudes from the casing through the opening. The pressing stem is movable parallel to a vertical direction relative to the casing through the first and second supports. A motion of the pressing stem in the vertical direction has a top dead center and a bottom dead center. When the pressing stem is at the top dead center and the bottom dead center, it does not touch the casing in the vertical direction.
    Type: Application
    Filed: July 18, 2023
    Publication date: March 28, 2024
    Applicant: DARFON ELECTRONICS CORP.
    Inventors: Yu-Chun Hsieh, Ling-Hsi Chao, Shao-Lun Hsiao, Chen Yang
  • Publication number: 20240107050
    Abstract: Provided are a picture encoding and decoding method, an encoder, a decoder and a storage medium. The decoder decodes a bitstream to obtain a size, a coding mode, and residuals of a current block; when the coding mode of the current block is an MIP mode, calculates a second offset based on the size of the current block, a first offset and reconstructed values of adjacent pixels corresponding to the current block; determines a first prediction value of the current block according to the second offset; and determines a reconstructed value of the current block based on the first prediction value.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Junyan HUO, Yanzhuo MA, Shuai WAN, Wei ZHANG, Fuzheng YANG, Haixin WANG, Yu SUN
  • Publication number: 20240105850
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 28, 2024
    Inventors: Che-Yu Yang, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20240106462
    Abstract: a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.
    Type: Application
    Filed: April 28, 2023
    Publication date: March 28, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-Yeol Yang, BOHWAN JUN, HONG RAK SON, GEUNYEONG YU, YOUNGJUN HWANG
  • Patent number: 11939603
    Abstract: A modified cutinase is disclosed. The cutinase has the modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of asparagine at position 181 with alanine, or substitutions of asparagine at position 181 with alanine and phenylalanine at position 235 with leucine. The modified enzyme has improved PET-hydrolytic activity, and thus, the high-activity PET hydrolase is obtained, and the industrial application value of the PET hydrolase is enhanced.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: March 26, 2024
    Assignee: HUBEI UNIVERSITY
    Inventors: Chun-Chi Chen, Jian-Wen Huang, Jian Min, Xian Li, Beilei Shi, Panpan Shen, Yu Yang, Yumei Hu, Longhai Dai, Lilan Zhang, Yunyun Yang, Rey-Ting Guo
  • Patent number: 11939238
    Abstract: The present disclosure provides an apparatus and a method for hydrate-based wastewater treatment and cold storage. The apparatus for hydrate-based wastewater treatment and cold storage includes a water chilling unit, a hydrate-based cold storage tank, an airflow disturbance device, a water layer positioning system, a spraying system, a suction filtration system, a heat exchange system, and a system monitoring device. The water chilling unit provides a secondary refrigerant at a low temperature. The secondary refrigerant flows through an evaporator coil in the hydrate-based cold storage tank for heat exchange. The airflow disturbance device induces hydrate nucleation. The water layer positioning system positions a contact surface between a water layer and a hydrate former after hydrate decomposition to facilitate drawing and separation of the treated upper water layer. The spraying system and the suction filtration system enhance the solid-liquid separation efficiency to improve the removal rate of pollutants.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: March 26, 2024
    Assignee: DALIAN UNIVERSITY OF TECHNOLOGY
    Inventors: Lunxiang Zhang, Yongchen Song, Xiaodong Wu, Jiazhu Bao, Chuanxiao Cheng, Zheng Ling, Jie Wang, Fan Wang, Yu Liu, Lei Yang, Mingjun Yang, Yanghui Li, Peng Wu
  • Patent number: 11940349
    Abstract: Disclosed is a plane grating calibration system, comprising an optical subsystem, a frame, first vibration isolator, a vacuum chuck, a workpiece stage, second vibration isolator, a base platform and a controller; the optical subsystem is mounted on the frame, and the frame is isolated from vibration by the first vibration isolator; the vacuum chuck is rotatably mounted on the workpiece stage, the workpiece stage is positioned on the base platform, and the base platform is isolated from vibration by the second vibration isolator. A displacement interferometer is integrated into the optical subsystem, and the entire optical subsystem adopts a method of sharing a light source, thereby avoiding the problems of low wavelength precision and poor coherence of separate light sources.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 26, 2024
    Assignees: TSINGHUA UNIVERSITY, BEIJING U-PRECISION TECH CO., LTD.
    Inventors: Leijie Wang, Ming Zhang, Yu Zhu, Jiankun Hao, Xin Li, Rong Cheng, Kaiming Yang, Jinchun Hu
  • Patent number: 11943877
    Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: March 26, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Wen-Yu Lin, Kai-Ming Yang, Chen-Hao Lin, Pu-Ju Lin, Cheng-Ta Ko, Chin-Sheng Wang, Guang-Hwa Ma, Tzyy-Jang Tseng
  • Patent number: 11941210
    Abstract: A detection circuit is provided herein, which includes a first transistor, a second transistor, a third transistor, a light sensor, a capacitor, and a fourth transistor. The first transistor has a control terminal, a first terminal, and a second terminal. The second transistor is coupled to the control terminal. The third transistor is coupled to the control terminal and the second terminal. The light sensor is coupled to the control terminal. The capacitor is coupled to the control terminal. The fourth transistor is coupled to the second terminal.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: March 26, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Ya-Li Tsai, Hui-Ching Yang, Yang-Jui Huang, Te-Yu Lee
  • Patent number: 11942358
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11942447
    Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Yang Chiou, Fu-Ting Yen, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11938567
    Abstract: A laser fusion welding device includes a 1.9 ?m laser light source, a control unit and a light spot adjusting device. The control unit is configured to control the laser light source and the light spot adjusting device to adjust a laser power density at an object to be subjected to fusion welding. The 1.9 ?m laser light source has output power of 100-500 W. The control unit includes a time control unit, a power control unit and a light spot control unit. The time control unit is configured to control a turn-on time of the laser light source. The power control unit is configured to control the output power of the laser light source. The light spot control unit is configured to control the light spot adjusting device to adjust a size of a light spot at the object to be subjected to fusion welding.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: March 26, 2024
    Assignee: XINJIANG TECHNICAL INSTITUTE OF PHYSICS AND CHEMISTRY, CHINESE ACADEMY OF SCIENCES
    Inventors: Linjun Li, Shilie Pan, Xiaoming Duan, Yu Zhou, Yingjie Shen, Qianqian Hao, Yuqiang Yang, Xin He