Patents by Inventor Yu-Yang Chang

Yu-Yang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12290005
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Grant
    Filed: May 30, 2024
    Date of Patent: April 29, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • Publication number: 20250123429
    Abstract: An electronic device is provided. The electronic device includes a panel, a protective substrate, and a first light-shielding structure. The panel has an active area and a peripheral area. The peripheral area is adjacent to the active area. The protective substrate is disposed opposite to the panel. The first light-shielding structure is disposed on a surface of the protective substrate and corresponds to the peripheral area. A portion of the first light-shielding structure that overlaps the peripheral area has at least one opening.
    Type: Application
    Filed: September 9, 2024
    Publication date: April 17, 2025
    Inventors: Yen-Chi CHANG, Min-Chien SUNG, Po-Tsun KUO, Yu-Kai WANG, Wei-Lun HSIAO, Cheng-Yang TSAI, Yu-Ting CHEN
  • Publication number: 20250121078
    Abstract: Disclosed are compounds of formula (I): in which L1, L2, LD1, LD2, R5, and R6 are defined. Also provided are pharmaceutical compositions containing such a compound a method of treating cancer using the compound.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 17, 2025
    Inventors: Lun Kelvin Tsou, Yu-Wei Liu, Chiung-Tong Chen, Tai-Yu Chiu, Chuan Shih, Jang-Yang Chang
  • Patent number: 12277977
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Grant
    Filed: May 13, 2024
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Publication number: 20250111821
    Abstract: A display apparatus is provided. The display apparatus includes a display module and multiple light-emitting driving circuits. Each of the light-emitting driving circuits includes a timing control circuit and a driving circuit. The timing control circuit receives multiple clock signals and a previous light-emitting timing signal to provide a light-emitting timing signal and an internal voltage. The driving circuit receives a first phase signal among multiple phase signals and the internal voltage to provide a light-emitting driving signal to the display module based on the first phase signal and the internal voltage. The phase signals all present disabled levels during a vertical blank period.
    Type: Application
    Filed: July 16, 2024
    Publication date: April 3, 2025
    Applicant: AUO Corporation
    Inventors: Che-Chia Chang, Che-Wei Tung, En-Chih Liu, Yu-Chieh Kuo, Mei-Yi Li, Ming-Hung Chuang, Yu-Hsun Chiu, Chen-Chi Lin, Cheng-Hsing Lin, Shu-Wen Tzeng, Jui-Chi Lo, Ming-Yang Deng
  • Publication number: 20250098196
    Abstract: The present invention relates to a semiconductor structure and a method for forming the same. The semiconductor structure comprises a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode, a drain electrode, and a cap layer. The channel layer is disposed on the substrate, the barrier layer is disposed on the channel layer, and the source electrode, the gate electrode, and the drain electrode are disposed on the barrier layer. Except the regions directly above the source electrode and the drain electrode, the cap layer covers the source electrode and the drain electrode.
    Type: Application
    Filed: April 4, 2024
    Publication date: March 20, 2025
    Inventors: Yu-Wei CHANG, Tzuen-Yang YE
  • Publication number: 20250061711
    Abstract: A method for automatically obtaining factors related to traffic accidents includes: in case that a traffic accident is identified in a traffic video, categorizing the traffic accident into one of a plurality of pre-determined categories; collecting, first factoring data and second factoring data contained in the traffic video within an accident-related time period, tagging the traffic video as a traffic accident video with the one of the pre-determined categories, and storing the traffic accident video, the first factoring data and the second factoring data in a data storage; compiling a factor group for the traffic accident video based on the first factoring data and the second factoring data, and aggregating a plurality of factor groups of traffic accident videos to create aggregated factor groups; and creating a spreadsheet that contains the aggregated factor groups and that can be sorted using geographical locations.
    Type: Application
    Filed: August 13, 2024
    Publication date: February 20, 2025
    Inventors: Chih-Pei LIU, Yu-Sheng CHANG, Hsiao-Yang Lee, Chuang-Chiang Dai
  • Patent number: 12232333
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Fei Chiu, Wen-Ting Chu, Yong-Shiuan Tsair, Yu-Wen Liao, Chih-Yang Chang, Chin-Chieh Yang
  • Publication number: 20250022938
    Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor structure. The method includes forming an active region over a substrate, forming a dummy gate layer over the active region, forming a hard mask layer over the dummy gate layer, forming a patterned photoresist over the hard mask layer, and performing an etching process to the hard mask layer and the dummy gate layer using the patterned photoresist, thereby forming patterned hard mask structures and patterned dummy gate structures. The patterned hard mask structures are formed with an uneven profile having a protruding portion. The protruding portion of each of the patterned hard mask structures has a first width, wherein each of the patterned dummy gate structures has a second width, and the first width is greater than the second width.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 16, 2025
    Inventors: Yao-Hsuan Lai, Hung-Ju Chou, Chih-Chung Chang, Wei-Yang Lee, Yu-Shan Lu, Yu-Ling Hsieh
  • Publication number: 20240047593
    Abstract: A thin film photovoltaic structure has a substrate, a first conductive layer, a photovoltaic layer, a second conductive layer, multiple serial connection conductive layers and multiple first insulating areas. By using the serial connection conductive layer, each width between each adjacent serially connected photovoltaic structures is reduced, and an effective area of the thin film photovoltaic structure for collecting optic energy is increased, thus enhancing a geometry fill factor of the thin film photovoltaic structure. Further, by using the serial connection conductive layer and the first insulating area to form contact overlap areas in an overlapping arrangement, it can effectively protect conductive areas in the first conductive layer when etching the second conductive layer during the manufacturing process, which prevents the conductive areas from being damaged to not act as electrodes, and efficiently increases a manufacture yielding rate of the thin film photovoltaic structure.
    Type: Application
    Filed: July 24, 2023
    Publication date: February 8, 2024
    Inventors: CHUNG-WEN KO, YU-FAN CHANG, YU-YANG CHANG, SUNG-CHIEN HUANG, HSIOU-MING LIU
  • Patent number: 11809667
    Abstract: A transparent conductive substrate structure used for a thermoforming process includes a transparent cover plate and a touch sensing layer structure. The transparent cover plate includes a toughening layer on one side thereof. The touch sensing layer structure arranged on one surface of the toughening layer, and includes a first transparent conductive layer, a dielectric layer, a barrier layer, a second transparent conductive layer, and a buffer protective layer. Each transparent conductive layer is directly applied to the transparent cover plate, so that the thickness between the transparent conductive layers is below 1 ?m. The thickness between layers may be reduced to increase the sensitivity of the touch sensing layer structure. To prevent each transparent conductive layer and an electrode wire layer from breaking during the thermoforming process, the transparent conductive substrate structure is combined with the buffer protective layer to strengthen the structure of each transparent conductive layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 7, 2023
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Sheng-Chieh Tsai, Yao-Zong Chen, Yu-Yang Chang, Hsiou-Ming Liu
  • Publication number: 20230142280
    Abstract: A capacitive sensing identification tag includes a substrate and a touch sensing layer disposed on one side of the substrate. The touch sensing layer includes high-sensing regions and low-sensing regions with different shapes. Both the high-sensing regions and the low-sensing regions have different stacked conductive layers and dielectric layers. A difference between the high-sensing regions and the low-sensing regions is that each of the high-sensing regions contains a dielectric layer, while each of the low-sensing regions does not. The capacitive sensing identification tag achieves an effect of sampling and identification of a touch panel by a capacitive sensing quantity that is different from a capacitive touch panel. And the capacitive sensing identification tag will not cause a difference in color or light transmittance between the high-sensing regions and the low-sensing regions, so there is no visible difference between the high-sensing regions and the low-sensing regions.
    Type: Application
    Filed: December 8, 2021
    Publication date: May 11, 2023
    Inventors: Te-Fong CHAN, Fu-Tien KU, Yu-Yang CHANG, Sung-Chien HUANG, Hsiou-Ming LIU
  • Publication number: 20220350443
    Abstract: A transparent conductive substrate structure used for a thermoforming process includes a transparent cover plate and a touch sensing layer structure. The transparent cover plate includes a toughening layer on one side thereof. The touch sensing layer structure arranged on one surface of the toughening layer, and includes a first transparent conductive layer, a dielectric layer, a barrier layer, a second transparent conductive layer, and a buffer protective layer. Each transparent conductive layer is directly applied to the transparent cover plate, so that the thickness between the transparent conductive layers is below 1 ?m. The thickness between layers may be reduced to increase the sensitivity of the touch sensing layer structure. To prevent each transparent conductive layer and an electrode wire layer from breaking during the thermoforming process, the transparent conductive substrate structure is combined with the buffer protective layer to strengthen the structure of each transparent conductive layer.
    Type: Application
    Filed: June 4, 2021
    Publication date: November 3, 2022
    Inventors: Sheng-Chieh TSAI, Yao-Zong CHEN, Yu-Yang CHANG, Hsiou-Ming LIU
  • Patent number: 11075351
    Abstract: A packaging structure with groove includes a substrate, a lower conductive layer, an optical element, a sealing layer and a barrier layer. The lower conductive layer is arranged on one face of the substrate. The optical element is arranged on one face of the lower conductive layer. The upper conductive layer is arranged on one face of the optical element. The packaging structure further comprises a groove defined on an inactive area of the optical element. The sealing layer is arranged on one face of the optical element and on one face of the upper conductive layer. The barrier layer is arranged on one face of the sealing layer. Because the groove is formed on inactive area of the optical element to enhance lateral sealing tightness, extended interface is provided between sealing layer/barrier layer and the substrate, thus enhance the water-resistant and gas-resistant property for package.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: July 27, 2021
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Shih-Wen Liao, Yu-Yang Chang
  • Patent number: 11013156
    Abstract: An EMI shielding film includes a flexible composite metal layer, a transparent insulating layer, and a conductive adhesive layer. The conductive adhesive layer is formed by removing a solvent from a conductive adhesive composition. The conductive adhesive composition includes an acrylate solution, a divalent acid ester solution, a plurality of conductive particles, and the solvent. The present disclosure further includes a method of manufacturing the EMI shielding film.
    Type: Grant
    Filed: August 15, 2020
    Date of Patent: May 18, 2021
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Sung-Chien Huang, Yu-Yang Chang, Hsiou-Ming Liu, Ping-Feng Yu
  • Publication number: 20200185631
    Abstract: A packaging structure with groove includes a substrate, a lower conductive layer, an optical element, a sealing layer and a barrier layer. The lower conductive layer is arranged on one face of the substrate. The optical element is arranged on one face of the lower conductive layer. The upper conductive layer is arranged on one face of the optical element. The packaging structure further comprises a groove defined on an inactive area of the optical element. The sealing layer is arranged on one face of the optical element and on one face of the upper conductive layer. The barrier layer is arranged on one face of the sealing layer. Because the groove is formed on inactive area of the optical element to enhance lateral sealing tightness, extended interface is provided between sealing layer/barrier layer and the substrate, thus enhance the water-resistant and gas-resistant property for package.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 11, 2020
    Inventors: Shih-Wen LIAO, Yu-Yang CHANG
  • Patent number: 10581004
    Abstract: A structure of photovoltaic cell is provided. The structure of photovoltaic cell includes a substrate, a lower conductive layer, a photovoltaic layer, and an upper conductive layer, the lower conductive layer is disposed at one side of the substrate, the photovoltaic layer is disposed at the other surface of the lower conductive layer, and the upper conductive layer is disposed on the other surface of the photovoltaic layer. An electron transporting layer, a hole transporting layer, and an active layer sandwiched between the electron transporting layer and the hole transporting layer collectively constitute the photovoltaic layer. The electron transporting layer convers a portion of the active layer and the hole transporting layer for blocking the upper conductive layer from electrically connecting to the active layer and the hole transporting layer.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 3, 2020
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Ding-Kuo Ding, Yu-Yang Chang, Shiou-Ming Liu, Sung-Chien Huang
  • Patent number: 10566559
    Abstract: A structure of photovoltaic cell is provided. The structure of photovoltaic cell includes a substrate, a lower conductive layer, a photovoltaic layer, and an upper conductive layer, the lower conductive layer is disposed at one side of the substrate, the photovoltaic layer is disposed at the other surface of the lower conductive layer, and the upper conductive layer is disposed on the other surface of the photovoltaic layer. An electron transporting layer, a hole transporting layer, and an active layer sandwiched between the electron transporting layer and the hole transporting layer collectively constitute the photovoltaic layer. The electron transporting layer covers a portion of the active layer and the hole transporting layer for blocking the upper conductive layer from electrically connecting to the active layer and the hole transporting layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: February 18, 2020
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Ding-Kuo Ding, Yu-Yang Chang, Shiou-Ming Liu, Sung-Chien Huang
  • Publication number: 20190221763
    Abstract: A structure of photovoltaic cell is provided. The structure of photovoltaic cell includes a substrate, a lower conductive layer, a photovoltaic layer, and an upper conductive layer, the lower conductive layer is disposed at one side of the substrate, the photovoltaic layer is disposed at the other surface of the lower conductive layer, and the upper conductive layer is disposed on the other surface of the photovoltaic layer. An electron transporting layer, a hole transporting layer, and an active layer sandwiched between the electron transporting layer and the hole transporting layer collectively constitute the photovoltaic layer. The electron transporting layer convers a portion of the active layer and the hole transporting layer for blocking the upper conductive layer from electrically connecting to the active layer and the hole transporting layer.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 18, 2019
    Inventors: Ding-Kuo DING, Yu-Yang CHANG, Shiou-Ming LIU, Sung-Chien Huang
  • Publication number: 20190074461
    Abstract: A structure of photovoltaic cell is provided. The structure of photovoltaic cell includes a substrate, a lower conductive layer, a photovoltaic layer, and an upper conductive layer, the lower conductive layer is disposed at one side of the substrate, the photovoltaic layer is disposed at the other surface of the lower conductive layer, and the upper conductive layer is disposed on the other surface of the photovoltaic layer. An electron transporting layer, a hole transporting layer, and an active layer sandwiched between the electron transporting layer and the hole transporting layer collectively constitute the photovoltaic layer. The electron transporting layer convers a portion of the active layer and the hole transporting layer for blocking the upper conductive layer from electrically connecting to the active layer and the hole transporting layer.
    Type: Application
    Filed: December 5, 2017
    Publication date: March 7, 2019
    Inventors: Ding-Kuo DING, Yu-Yang CHANG, Shiou-Ming LIU, Sung-Chien Huang