Patents by Inventor Yu-Yang Chang

Yu-Yang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385527
    Abstract: A control system includes a plurality of pressure sensors, each to detect a pressure in a respective dynamic gas lock (DGL) nozzle control region of a plurality of DGL nozzle control regions. Each DGL nozzle control region includes one or more DGL nozzles. The control system includes a plurality of mass flow controllers (MFCs). Each MFC of the plurality of MFCs is to control a flow velocity in a respective DGL nozzle control region of the plurality of DGL nozzle control regions. The control system includes a controller to selectively cause one or more MFCs of the plurality of MFCs to adjust flow velocities in one or more DGL nozzle control regions of the plurality of DGL nozzle control regions based on pressures detected by the plurality of pressure sensors in DGL nozzle control regions of the plurality of DGL nozzle control regions.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chun-Kai CHANG, Yu Sheng CHIANG, Yu De LIOU, Chi YANG, Ching-Juinn HUANG, Po-Chung CHENG
  • Publication number: 20240389213
    Abstract: A dispensing system includes a dispense material supply that contains a dispense material and a dispensing pump connected downstream from the dispense material supply. The dispensing pump includes a body made of a first electrically conductive material, one or more first electrical contacts that are disposed on the body of the dispensing pump, and one or more first connection wires that are coupled between each one of the one or more first electrical contacts and ground. The dispensing system also includes a dispensing nozzle connected downstream from the dispensing pump and includes a tube made of a second electrically conductive material, one or more second electrical contacts that are disposed on an outer surface of the tube, and one or more second connection wires that are coupled between each one of the one or more second electrical contacts and the ground.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yang LIN, Yu-Cheng CHANG, Cheng-Han WU, Shang-Sheng LI, Chen-Yu LIU, Chen Yi HSU
  • Patent number: 12137534
    Abstract: A hardware-based fan controller for controlling fan modules in a computer system having multiple computer nodes is disclosed. Each of the computer nodes has a service processor. The fan controller includes a slave module that receives fan speed commands from each of the service processors. A fan speed generator is coupled to the slave module and a subset of the fan modules. The fan speed generator receives fan speed commands from the slave module and fan speed outputs from the subset of fan modules. The fan speed generator is configured to output a speed command to each of the fan modules in the subset.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 5, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Hsien-Yang Cheng, Ying-Che Chang, Yi-An Chen, Yu-Tang Zeng
  • Publication number: 20240363725
    Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes forming a semiconductor fin over a substrate, forming an integral dielectric layer over the substrate, wherein the dielectric layer includes a first portion extending along a sidewall surface of the semiconductor fin and a second portion disposed over the semiconductor fin, a thickness of the second portion of the dielectric layer is greater than a thickness of the first portion of the dielectric layer, forming a dummy gate electrode layer over the substrate, patterning the dielectric layer and the dummy gate electrode layer to form a dummy gate structure over a channel region of the semiconductor fin, forming source/drain features coupled to the channel region of the semiconductor fin and adjacent to the dummy gate structure, and replacing the dummy gate structure with a gate stack.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Yu-Ling Hsieh, Hung-Ju Chou, Yu-Shan Lu, Wei-Yang Lee, Chih-Chung Chang, Yao-Hsuan Lai
  • Patent number: 12125956
    Abstract: A semiconductor device is provided, which includes a semiconductor stack and a first contact structure. The semiconductor stack includes an active layer and has a first surface and a second surface. The first contact structure is located on the first surface and includes a first semiconductor layer, a first metal element-containing structure and a first p-type or n-type layer. The first metal element-containing structure includes a first metal element. The first p-type or n-type layer physically contacts the first semiconductor layer and the first metal element-containing structure. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm, and the first semiconductor layer includes a phosphide compound or an arsenide compound.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: October 22, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Yu-Tsu Lee, Yi-Yang Chiu, Chun-Wei Chang, Min-Hao Yang, Wei-Jen Hsueh, Yi-Ming Chen, Shih-Chang Lee, Chung-Hao Wang
  • Patent number: 12105907
    Abstract: A display panel and an operation method of the display panel are provided. The display panel includes a display area and a frame area. The display area is configured to display an image. During a touch sensing period, the display area and the frame area emit an uplink signal to perform an active stylus touch detection operation.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: October 1, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yu-Ying Tang, Wei-Ren Chang, Chih-Yang Ke, Chih-Chang Lai
  • Patent number: 12107333
    Abstract: This invention provides an antenna assembly equipped with a sub-wavelength structured enhancer, comprising an antenna supporting substrate with a top surface and a bottom surface opposite to each other; a first patch antenna is disposed on the top surface of the antenna supporting substrate or inside of the antenna supporting substrate; a ground layer is disposed under the bottom surface of the antenna supporting substrate; a signal feeding layer for transmitting satellite communicating signals is disposed on one of surfaces of the antenna supporting substrate, or inside of the antenna supporting substrate, or under the first patch antenna, or under a side of the ground layer back to the antenna supporting substrate; and a solid sub-wavelength structured enhancer is disposed above the first patch antenna and spaced with each other by an air gap ranging between 7 mm and 47 mm.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: October 1, 2024
    Assignee: AuthenX Inc.
    Inventors: Yu-Chun Wang, Po-Kuan Shen, Sheng-Fu Lin, Jenq-Yang Chang, Mao-Jen Wu
  • Publication number: 20240324472
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • Patent number: 12100576
    Abstract: Embodiments of process kits for use in a process chamber are provided herein. In some embodiments, a process kit for use in a process chamber includes: a chamber liner having a tubular body with an upper portion and a lower portion; a confinement plate coupled to the lower portion of the chamber liner and extending radially inward from the chamber liner, wherein the confinement plate includes a plurality of slots; a shield ring disposed within the chamber liner and movable between the upper portion of the chamber liner and the lower portion of the chamber liner; and a plurality of ground straps coupled to the shield ring at a first end of each ground strap of the plurality of ground straps and to the confinement plate at a second end of each ground strap to maintain electrical connection between the shield ring and the chamber liner when the shield ring moves.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 24, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Andrew Nguyen, Xue Yang Chang, Yu Lei, Xianmin Tang, John C. Forster, Yogananda Sarode Vishwanath, Abilash Sainath, Tza-Jing Gung
  • Patent number: 12087579
    Abstract: A method for forming a semiconductor device includes receiving a substrate having a first opening and a second opening formed thereon, wherein the first opening has a first width, and the second opening has a second width less than the first width; forming a protecting layer to cover the first opening and expose the second opening; performing a wet etching to widen the second opening with an etchant, wherein the second opening has a third width after the performing of the wet etching, and the third width of the second opening is substantially equal to the first width of the first opening; and performing a photolithography to transfer the first opening and the second opening to a target layer.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yang Huang, Hao-Ming Chang, Ming Che Li, Yu-Hsin Hsu, Po-Cheng Lai, Kuan-Shien Lee, Wei-Hsin Lin, Yi-Hsuan Lin, Wang Cheng Shih, Cheng-Ming Lin
  • Patent number: 12085861
    Abstract: A control system includes a plurality of pressure sensors, each to detect a pressure in a respective dynamic gas lock (DGL) nozzle control region of a plurality of DGL nozzle control regions. Each DGL nozzle control region includes one or more DGL nozzles. The control system includes a plurality of mass flow controllers (MFCs). Each MFC of the plurality of MFCs is to control a flow velocity in a respective DGL nozzle control region of the plurality of DGL nozzle control regions. The control system includes a controller to selectively cause one or more MFCs of the plurality of MFCs to adjust flow velocities in one or more DGL nozzle control regions of the plurality of DGL nozzle control regions based on pressures detected by the plurality of pressure sensors in DGL nozzle control regions of the plurality of DGL nozzle control regions.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Kai Chang, Yu Sheng Chiang, Yu De Liou, Chi Yang, Ching-Juinn Huang, Po-Chung Cheng
  • Publication number: 20240296890
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Publication number: 20240297126
    Abstract: An electronic package is provided in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure is embedded in the packaging layer. Therefore, thermal stress is dispersed through the frame body to avoid warpage of the electronic package, so as to facilitate the arrangement of other electronic components around the electronic component.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 5, 2024
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chien-Cheng LIN, Ko-Wei CHANG, Yu-Wei YEH, Shun-Yu CHIEN, Chia-Yang CHEN
  • Patent number: 12063070
    Abstract: A wireless radio frequency conversion system is disclosed. The wireless radio frequency conversion system includes a primary distributing device, a one-to-many conversion device, a plurality of first optical fiber networks, a plurality of remote antenna devices, and a plurality of antennas. The primary distributing device is configured to receive a first photoelectric signal. The one-to-many conversion device is configured to perform an optical-electrical conversion and a one-to-many conversion to the first photoelectric signal so as to generate a plurality of second photoelectric signals. The plurality of first optical fiber networks are configured to transmit the plurality of second photoelectric signals. The plurality of remote antenna devices are configured to receive and perform an optical-electrical conversion to the plurality of second photoelectric signals so as to generate a plurality of third photoelectric signals.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: August 13, 2024
    Inventors: Po-Kuan Shen, Yu-Chun Wang, Kai-Lun Han, Jenq-Yang Chang, Mao-Jen Wu
  • Patent number: 12057409
    Abstract: An electronic package and a manufacturing method of the electronic package are provided, in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure nor cover the electronic component is embedded in the packaging layer.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: August 6, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Chien-Cheng Lin, Ko-Wei Chang, Yu-Wei Yeh, Shun-Yu Chien, Chia-Yang Chen
  • Patent number: 12057884
    Abstract: A wireless radio frequency conversion system is disclosed. The baseband device generates or receives a baseband signal. The remote radio device transforms between the baseband signal and a radio frequency signal. The beamforming device adjusts amplitude and phase of the radio frequency signal or adjusts scale factor and phase factor of the baseband signal. The conversion device performs an optical-electrical conversion to the radio frequency signal. One of the beamforming device, the conversion device, and the wireless radio frequency conversion system having a one-to-many conversion device performs a one-to-many conversion to the radio frequency signal or the baseband signal to generate radio frequency signals or baseband signals, or performs a many-to-one conversion to the radio frequency signals or the baseband signals to generate the radio frequency signal or the baseband signal. The front-end module amplifies the radio frequency signal. The antenna transmits or receives the radio frequency signal.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: August 6, 2024
    Inventors: Po-Kuan Shen, Yu-Chun Wang, Kai-Lun Han, Jenq-Yang Chang, Mao-Jen Wu
  • Publication number: 20240242016
    Abstract: A layout routing method includes determining a routing pattern according to a swapping rule, a via pattern, area constraints and pin locations; optimizing swapping in differential pairs according to the routing pattern; extracting features of each routing net to obtain extracted features; using an unsupervised algorithm to generate different routing groups according to the extracted features; and determining a routing order of the routing groups according to complex features of the routing groups.
    Type: Application
    Filed: December 25, 2023
    Publication date: July 18, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chih-Jung Hsu, Chen Lien, Deng-Yao Tu, Po-Yang Chen, Guan-Qi Fang, Shu-Huan Chang, Yi-Hung Chen, Yao-Chun Su, Yu-Yang Chen
  • Publication number: 20240047593
    Abstract: A thin film photovoltaic structure has a substrate, a first conductive layer, a photovoltaic layer, a second conductive layer, multiple serial connection conductive layers and multiple first insulating areas. By using the serial connection conductive layer, each width between each adjacent serially connected photovoltaic structures is reduced, and an effective area of the thin film photovoltaic structure for collecting optic energy is increased, thus enhancing a geometry fill factor of the thin film photovoltaic structure. Further, by using the serial connection conductive layer and the first insulating area to form contact overlap areas in an overlapping arrangement, it can effectively protect conductive areas in the first conductive layer when etching the second conductive layer during the manufacturing process, which prevents the conductive areas from being damaged to not act as electrodes, and efficiently increases a manufacture yielding rate of the thin film photovoltaic structure.
    Type: Application
    Filed: July 24, 2023
    Publication date: February 8, 2024
    Inventors: CHUNG-WEN KO, YU-FAN CHANG, YU-YANG CHANG, SUNG-CHIEN HUANG, HSIOU-MING LIU
  • Patent number: 11809667
    Abstract: A transparent conductive substrate structure used for a thermoforming process includes a transparent cover plate and a touch sensing layer structure. The transparent cover plate includes a toughening layer on one side thereof. The touch sensing layer structure arranged on one surface of the toughening layer, and includes a first transparent conductive layer, a dielectric layer, a barrier layer, a second transparent conductive layer, and a buffer protective layer. Each transparent conductive layer is directly applied to the transparent cover plate, so that the thickness between the transparent conductive layers is below 1 ?m. The thickness between layers may be reduced to increase the sensitivity of the touch sensing layer structure. To prevent each transparent conductive layer and an electrode wire layer from breaking during the thermoforming process, the transparent conductive substrate structure is combined with the buffer protective layer to strengthen the structure of each transparent conductive layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 7, 2023
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Sheng-Chieh Tsai, Yao-Zong Chen, Yu-Yang Chang, Hsiou-Ming Liu
  • Patent number: D1044027
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: September 24, 2024
    Assignee: E-LINK PLASTIC & METAL INDUSTRIAL CO., LTD.
    Inventors: Pin-Yang Chang, Yu Chin Hsu