Patents by Inventor Yu-Yang Chang

Yu-Yang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070092682
    Abstract: A recordable medium includes an inscription layer and at least one contrast inverting layer. The inscription layer has at least a first sub-layer and a second sub-layer that combine upon application of a write power. The inscription layer has a reflectivity R1 with respect to a read beam before application of the write power and a reflectivity R2 after application of the write power, and R1<R2. The at least one contrast inverting layer does not combine with the first and second sub-layers of the inscription layer upon application of the write power. The at least one contrast inverting layer and the inscription layer together have a reflectivity R3 before application of the write power and a reflectivity R4 after application of the write power, and R3>R4.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventors: Geoffrey Shuy, Cheng-Ji Lu, Hsin-Cheng Lai, Fang-Yu Lee, Yu-Yang Chang
  • Publication number: 20070046866
    Abstract: A field emission display module. A white field emission display (FED) comprises a plurality of dots (pixels) arranged in matrix, generating different gray levels according to external display data. A color filter display is disposed on the white field emission display, generating color images with the gray levels generated by the white field emission display.
    Type: Application
    Filed: November 18, 2005
    Publication date: March 1, 2007
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cheng-Chung Lee, Yu-Yang Chang, Liang-You Jiang, Yau-Chen Jiang, Lih-Hsiung Chan
  • Publication number: 20070049154
    Abstract: A method of fabricating a field emission display device and a cathode plate thereof is provided. By using a sandblasting process, an electrode layer on the cathode plate is patterned and a portion of the substrate fogged up to produce light diffusion effects. Since the electrodes and the light diffusion layer are formed in the same step, the process of fabricating the cathode plate is simplified.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 1, 2007
    Inventors: Yu-Yang Chang, Wei-Yi Lin, Kwan-Sin Ho, Te-Hao Tsou
  • Publication number: 20070035230
    Abstract: This invention provides an anode plate structure for a flat panel light source of field emission. The structure for the flat panel light source includes an anode plate structure in addition to a known cathode plate structure. The anode plate structure comprises an anode plate and a fluorescent layer formed on the anode plate. The flat panel light source utilizes a cubic-bump structure of the fluorescent layer or a rough surface of the anode plate to increase the lighting areas per unit volume, thereby enhancing the lighting effect of the light source. In the embodiments of the flat panel light source, the rough surface of the anode plate may be formed with a plurality of cubic-bumps, or have a shape of plural concave lenses.
    Type: Application
    Filed: February 17, 2006
    Publication date: February 15, 2007
    Inventors: Ming-Hung Lin, Yu-Yang Chang, Wei-Yi Lin, Cheng-Chung Lee
  • Publication number: 20070035941
    Abstract: Disclosed are a method for improving the uniformity of a flat panel light source and the light source thereof. It achieves a diffusion effect by blurring the lighting surface of the light module, thereby makes the outgoing lights more uniform. The blurring process can be performed on the inner or outer surface of a lighting substrate before a flat panel light source is assembled. Otherwise, the blurring process may be performed on an outer surface of an assembled light module. The invention is applicable to a field emission display (FED) back-light or front-light module. The lighting surface of a cathode plate module is blurred for an FED back-light source, and the lighting surface of an anode plate module for an FED front-light source.
    Type: Application
    Filed: October 19, 2005
    Publication date: February 15, 2007
    Inventors: Cheng-Chung Lee, Wei-Yi Lin, Yu-Yang Chang, Biing-Nan Lin
  • Patent number: 7161289
    Abstract: A triode structure of a field emission display and fabrication method thereof. A plurality of cathode layers arranged in a matrix is formed overlying a dielectric layer. A plurality of emitting layers arranged in a matrix is formed overlying the cathode layers, respectively. A plurality of lengthwise-extending gate lines is formed on the dielectric layer, in which each of the gate layers is disposed between two adjacent columns of the cathode layers.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: January 9, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Tao Lee, Cheng-Chung Lee, Jyh-Rong Sheu, Yu-Yang Chang, Jia-Chong Ho, Yu-Wu Wang
  • Patent number: 7156715
    Abstract: A triode structure of a field emission display and fabrication method thereof. A plurality of cathode layers arranged in a matrix is formed overlying a dielectric layer. A plurality of emitting layers arranged in a matrix is formed overlying the cathode layers, respectively. A plurality of lengthwise-extending gate lines is formed on the dielectric layer, in which each of the gate layers is disposed between two adjacent columns of the cathode layers.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: January 2, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Tao Lee, Cheng-Chung Lee, Jyh-Rong Sheu, Yu-Yang Chang, Jia-Chong Ho, Yu-Wu Wang
  • Patent number: 7154214
    Abstract: A structure of a coplanar gate-cathode of triode CNT-FED and a manufacturing method thereof by Imprint Lithography and ink jet. The structure includes a substrate, a plurality of cathode layers, a plurality of gate extended layers, a plastic dielectric layer, a plurality of dielectric openings, and a plurality of gate electrodes. The plurality of cathode layers and the plurality of gate extended layers are coplanar, and formed on the substrate by Imprint Lithography and the plurality of dielectric openings are made by Imprint Lithography. The gate electrode, made by ink jet or screen print, can be extended through the plastic dielectric layer to the gate extended electrode to feature the coplanar gate-cathode.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: December 26, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Ching-Hsun Chao, Jane-Hway Liao, Jyh-Rong Sheu, Yu-Yang Chang, Cheng-Chung Lee
  • Publication number: 20060258252
    Abstract: The present inventions provide a structure of coplanar gate-cathode of triode CNT-FED and the manufacturing method thereof by Imprint Lithography and ink jet. The structure includes a substrate, a plurality of cathode layers, a plurality of gate extended layers, a plastic dielectric layer, a plurality of dielectric openings, and a plurality of gate electrodes. The plurality of cathode layers and the plurality of gate extended layers are coplanar, made by forming on the substrate by Imprint Lithography and the plurality of dielectric opening made by Imprint Lithography too. Besides, the gate electrode, made by ink jet or screen print, can be extended through the plastic dielectric layer to the gate extended electrode to feature the coplanar gate-cathode.
    Type: Application
    Filed: July 21, 2006
    Publication date: November 16, 2006
    Inventors: Ching-Hsun Chao, Jane-Hway Liao, Jyh-Rong Sheu, Yu-Yang Chang, Cheng-Chung Lee
  • Publication number: 20060249388
    Abstract: The invention provides an electrophoretic deposition method of CNTs for a field emission device. It uses a triode structure having gates and a proper arrangement of applied voltages to improve the selectivity of the conventional EPD method. The electric field around the gates repels the charged or polarized nanostructure suspension in the electrophoresis bath and prevents the charged or polarized nanostructure materials from depositing in the neighborhood of the gates. Therefore, the nanostructure materials are selectively deposited on the cathode. An electrical short circuit between the gates and the cathodes can be avoided. It does not require a masked sacrificial layer, and therefore keeps the manufacturing process simple and the cost down.
    Type: Application
    Filed: May 4, 2005
    Publication date: November 9, 2006
    Inventors: Yu-Yang Chang, Lih-Hsiung Chan, Kwan-Sin Ho
  • Publication number: 20060238105
    Abstract: A triode field emission display is provided. It utilizes the electrical characteristics that an edge structure may raise the electric field intensity to expose an edge of a cathode plate through an opening of a gate layer, thereby forming the edge structure at an emitter to raise the electric field intensity. Therefore, reduction of driving voltage is achieved.
    Type: Application
    Filed: August 3, 2005
    Publication date: October 26, 2006
    Inventors: Biing-Nan Lin, Cheng-Chung Lee, Yu-Yang Chang, Wei-Yi Lin
  • Publication number: 20060238104
    Abstract: A quadrode field emission display is provided, where a low driving voltage is reached by an edge structure, and display in the dark is achieved by adding a sub-gate electrode. With respect to the electrical characteristics that an edge structure may raise the electric field intensity, an edge of a cathode plate through an opening of a gate layer is exposed, thereby forming the edge structure at an emitter to raise the electric field. It also reduces the driving voltage substantially. Therefore, the display in the dark is achieved by adjusting the voltage without changing the structure.
    Type: Application
    Filed: August 11, 2005
    Publication date: October 26, 2006
    Inventors: Biing-Nan Lin, Cheng-Chung Lee, Yu-Yang Chang, Wei-Yi Lin
  • Publication number: 20060232187
    Abstract: A field emission device includes a first substrate, a second substrate spaced apart from the first substrate, a cathode structure formed between the first substrate and the second substrate for emitting electrons toward the second substrate, a luminescent layer formed between the first substrate and the second substrate for providing light when the electrons impinge thereon, and a reflecting layer formed between the second substrate and the luminescent layer for reflecting the light toward the first substrate.
    Type: Application
    Filed: April 19, 2005
    Publication date: October 19, 2006
    Inventors: Biing-Nan Lin, Cheng-Chung Lee, Yu-Yang Chang, Chun-Tao Lee
  • Patent number: 7090555
    Abstract: A field emission display (FED) having a grid plate with spacer structure and fabrication method thereof. A first wplate having first electrodes and electron emitters on a first surface is provided. A second plate having second electrodes and phosphor regions on a second surface is also provided, wherein the second surface is opposite the first surface. A grid plate with spacer structure and passages having grid electrodes is positioned between the two plates to maintain a predetermined interval. When a specific voltage is applied between the first electrode and the second electrode, electrons extracted from the electron emitters are accelerated by the grid electrodes through the passages to impact the phosphor regions.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: August 15, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Tao Lee, Ming-Chun Hsiao, Wei-Yi Lin, Yu-Yang Chang, Yu-Wu Wang
  • Publication number: 20060175954
    Abstract: A planar light unit provided with field emitters and a method for fabricating the same. According to the present invention, the planar light unit has a first substrate, a plurality of first conductive strips, a plurality of second conductive strips, a plurality of field emitters, a second substrate and a fluorescent film. The plurality of first conductive strips are formed over the first substrate, and the plurality of second conductive strips are formed over the first substrate and interposed inbetween the plurality of first conductive strips. The plurality of field emitters are formed in proximity of the plurality of first conductive strips. The second substrate is provided to be attached to and spaced apart from the first substrate to form a chamber therebetween, whereas a fluorescent film is formed over the interior surface of the second substrate facing the plurality of field emitters.
    Type: Application
    Filed: February 4, 2005
    Publication date: August 10, 2006
    Inventors: Liang-You Chiang, Jyh-Rong Sheu, Yu-Yang Chang, Cheng-Chung Lee
  • Patent number: 7009331
    Abstract: A carbon nano-tube field emission display has a plurality of strip shaped gates, wherein the strip shaped gate of the triode structure is in place of the conventional hole shaped gate, and morecover, a plurality of cathode electrons are induced by the electric force from the side of the gate. Therefore, when the carbon nano-tube electron emission source emits electrons, which are controlled under the strip shaped gate, the diffusion direction of the electron beam is confined in the same direction. Consequently, controlling the image pixel and using the particular advantage of the triode-structure field emission display significantly improve the image uniformity and the luminous efficiency.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: March 7, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Jyh-Rong Sheu, Chun-Tao Lee, Shin-Chiuan Jiang, Yu-Yang Chang, Cheng-Chung Lee
  • Patent number: 7005787
    Abstract: This invention is an improved processing method and structure for the packaging technique of a large size field emission display. A large size field emission display includes an indium-tin oxides (ITO) conducting glass substrate, which is covered by the first screen mask and the second screen mask defined to a BM layer area, a multi-phosphor layer area and a hollow area. Each area was coated to form an Al layer, which was formed an AlOx layer through a phosphor sintering process. The spacer was fixed in a hollow area of an AlOx layer through an anodic assembling technique. The next plate was fixed on the spacer to accomplish an aligner process.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: February 28, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Chun Hsiao, Cheng-Chung Lee, Yu-Yang Chang
  • Publication number: 20050275338
    Abstract: A field emission display (FED) having a grid plate with spacer structure and fabrication method thereof. A first plate having first electrodes and electron emitters on a first surface is provided. A second plate having second electrodes and phosphor regions on a second surface is also provided, wherein the second surface is opposite the first surface. A grid plate with spacer structure and passages having grid electrodes is positioned between the two plates to maintain a predetermined interval. When a specific voltage is applied between the first electrode and the second electrode, electrons extracted from the electron emitters are accelerated by the grid electrodes through the passages to impact the phosphor regions.
    Type: Application
    Filed: August 22, 2005
    Publication date: December 15, 2005
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Tao Lee, Ming-Chun Hsiao, Wei-Yi Lin, Yu-Yang Chang, Yu-Wu Wang
  • Publication number: 20050253501
    Abstract: The present inventions provide a structure of coplanar gate-cathode of triode CNT-FED and the manufacturing method thereof by Imprint Lithography and ink jet. The structure includes a substrate, a plurality of cathode layers, a plurality of gate extended layers, a plastic dielectric layer, a plurality of dielectric openings, and a plurality of gate electrodes. The plurality of cathode layers and the plurality of gate extended layers are coplanar, made by forming on the substrate by Imprint Lithography and the plurality of dielectric opening made by Imprint Lithography too. Besides, the gate electrode, made by ink jet or screen print, can be extended through the plastic dielectric layer to the gate extended electrode to feature the coplanar gate-cathode.
    Type: Application
    Filed: June 9, 2004
    Publication date: November 17, 2005
    Inventors: Ching-Hsun Chao, Jane-Hway Liao, Jyh-Rong Sheu, Yu-Yang Chang, Cheng-Chung Lee
  • Publication number: 20050197032
    Abstract: A triode structure of a field emission display and fabrication method thereof. A plurality of cathode layers arranged in a matrix is formed overlying a dielectric layer. A plurality of emitting layers arranged in a matrix is formed overlying the cathode layers, respectively. A plurality of lengthwise-extending gate lines is formed on the dielectric layer, in which each of the gate layers is disposed between two adjacent columns of the cathode layers.
    Type: Application
    Filed: April 19, 2005
    Publication date: September 8, 2005
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Tao Lee, Cheng-Chung Lee, Jyh-Rong Sheu, Yu-Yang Chang, Jia-Chong Ho, Yu-Wu Wang