Patents by Inventor Yu Yang

Yu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395391
    Abstract: Methods of forming electronic devices and film stacks comprising depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide and patterned photoresist are formed, and the pattern of the patterned photoresist are transferred into the ruthenium carbide hard mask. Film stacks comprising the ruthenium carbide hard mask on the capacitor mold are also described.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 7, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Han Wang, Gene H. Lee, Yu Yang, Jing Zhang
  • Publication number: 20230395119
    Abstract: A refresh address counting circuit, a refresh address counting method, and a refresh address read-write circuit are provided. The refresh address counting circuit includes: a self-oscillation clock generation circuit, configured to generate, in each of refresh cycles, a self-oscillation clock signal based on at least one array activation signal upon acquiring a refresh signal; a self-oscillation mask circuit, configured to generate a self-oscillation mask signal under a preset refresh command; and a refresh address counter, configured to counting a refresh address based on the self-oscillation clock signal and the self-oscillation mask signal and to output a self-oscillation refresh address.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 7, 2023
    Inventors: Xian FAN, Yinchuan Gu, Xianlei Cao, Yu Yang, Hsin-Cheng Su
  • Patent number: 11837995
    Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: December 5, 2023
    Assignee: MEDIATEK INC.
    Inventors: Hao-Wei Huang, Song-Yu Yang, Ang-Sheng Lin, Yi-Chien Tsai
  • Publication number: 20230387250
    Abstract: An HEMT with a stair-like compound layer as a drain includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode, a gate electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed between the source electrode and the drain electrode. A first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer. The first P-type III-V compound layer is stair-like.
    Type: Application
    Filed: June 17, 2022
    Publication date: November 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11832536
    Abstract: A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: November 28, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Publication number: 20230379897
    Abstract: A beam indication method includes receiving, by a terminal, a first signaling, the first signaling being used for indicating a TCI state, the TCI state being used for indicating a common beam of at least two channels or reference signals; and transmitting feedback information of the first signaling, the feedback information of the first signaling including one of feedback information of a first target channel, a second target channel and a target reference signal.
    Type: Application
    Filed: July 12, 2023
    Publication date: November 23, 2023
    Inventor: Yu Yang
  • Publication number: 20230378006
    Abstract: Methods and systems for monitoring wafer processing results continuously and in real-time. In some embodiments, a system may comprise at least one non-active chamber with at least one feedthrough access port which is configured to interact with a metrology apparatus. The feedthrough access port has a surface exposed to an inner volume of the non-active chamber and has a fluorine-based coating covering the surface. The non-active chamber has a wafer access port to one or more other chambers. The metrology apparatus is positioned external to the non-active chamber and is oriented to detect metrology data through one of the feedthrough access ports. A data collection apparatus is connected to the metrology apparatus and configured to continuously receive data from the metrology apparatus.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Shuran SHENG, Eric HOLLAR, Sock Hoon LIM, Yu YANG, Ralph P. ANTONIO, Gu LIU
  • Publication number: 20230378948
    Abstract: Delay circuitry includes a temperature compensation control circuit and a delay circuit. The temperature compensation control circuit is configured to generate a target temperature compensation control signal based on an initial control signal, a real-time ambient temperature signal, a temperature coefficient compensation enable signal, and a temperature coefficient control signal. The delay circuit is connected to the temperature compensation control circuit, and is configured to generate a temperature compensated target delay signal based on the target temperature compensation control signal and an initial delay signal such that a delay time of the target delay signal generated by the delay circuit can be dynamically compensated based on a real-time ambient temperature signal collected by a temperature sensor.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventor: Yu YANG
  • Patent number: 11825363
    Abstract: A resource processing method, an apparatus, and a system are disclosed. The resource processing method comprises: receiving, by UE, first signaling from a base station, wherein the first signaling is used to instruct to deactivate a first cell that provides a service for the UE, or used to instruct the UE to switch from a source bandwidth part (BWP) to a target BWP; and processing, by a media access control (MAC) entity in the UE, a first target resource by using a first target processing manner, wherein the first target resource is a resource in the first cell or the source BWP.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: November 21, 2023
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Yu Yang, Peng Sun
  • Patent number: 11821847
    Abstract: A wafer backside defect detection method and a wafer backside defect detection apparatus are provided. The wafer backside defect detection method includes the following steps. A peripheral edge area of a wafer backside image that at least one notch is located is cropped off. Adjacent white pixels on the wafer backside image are connected to obtain a plurality of abnormal regions. If a total area of top N of the abnormal regions is more than 10% of an area of the wafer, it is deemed that the wafer has a roughness defect. N is a natural number. If the total area of the top N of the abnormal regions is less than 1% of the area of the wafer and a largest abnormal region of the abnormal regions is longer than a predetermined length, it is deemed that the wafer has a scratch defect.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: November 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hsien Chen, Chia-Feng Hsiao, Chung-Hsuan Wu, Chen-Hui Huang, Nai-Ying Lo, En-Wei Tsui, Yung-Yu Yang, Chen-Hsuan Hung
  • Publication number: 20230369481
    Abstract: A method for forming a high electron mobility transistor includes the steps of forming an epitaxial stack on a substrate, forming a gate structure on the epitaxial stack, forming an insulating layer covering the epitaxial stack and the gate structure, forming a passivation layer on the insulating layer, forming an opening on the gate structure and through the passivation layer to expose the insulating layer, and removing a portion of the insulating layer through the opening to form an air gap between the gate structure and the passivation layer.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Yu Yang, Hsun-Wen Wang
  • Patent number: 11817470
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang, Wei-Chih Weng, Yu-Yang Shen
  • Publication number: 20230361843
    Abstract: A beam indication method, a network device, and a terminal device are provided. The method includes: receiving a first command sent by the network device. The first command is used to indicate at least one Transmission Configuration Indication (TCI) state in a TCI state pool. The at least one TCI state comprises a joint TCI state or a separate TCI state. The TCI state pool is preconfigured by the network device. The at least one TCI state is used to indicate common beam information of a plurality of channels or Reference Signals (RSs). The method further includes determining, according to the first command, the at least one TCI state corresponding to an Uplink (UL) or a Downlink (DL).
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Applicant: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventor: Yu YANG
  • Publication number: 20230359592
    Abstract: In an approach, a processor obtains a configuration file of a distributed file system federation, the configuration file comprising a list of a plurality of subclusters within the distributed file system federation and migration trigger factors for the plurality of subclusters. A processor determines a list of one or more source subclusters and a list of to-be-migrated directories in the one or more source subclusters based on a scanning result of the plurality of subclusters and the migration trigger factors in the configuration file. A processor generates a migration plan to migrate the to-be-migrated directories from the one or more source subclusters to one or more target subclusters in the distributed file system federation.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 9, 2023
    Inventors: Jun Guo, Xiang Yu Yang, Deng Xin Luo, Na Liu, Chen Yu Chang, Qin Dong Yin
  • Patent number: 11810300
    Abstract: This application provides a method for detecting images of testing object using hyperspectral imaging. Firstly, obtaining a hyperspectral imaging information according to a reference image, hereby, obtaining corresponded hyperspectral image from an input image and obtaining corresponded feature values for operating Principal components analysis to simplify feature values. Then, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the esophageal cancer sample image, the image of the object under detected is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the image of the object under detected.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: November 7, 2023
    Assignee: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Tsung-Yu Yang, Yu-Sheng Chi, Ting-Chun Men
  • Patent number: 11811480
    Abstract: Embodiments of the disclosure relate to the field of communications technologies, and disclose a method for transmitting a beam failure recovery request, a terminal device, and a network device. The method includes: determining, by a terminal device, that a beam failure event has occurred in a first cell, where the first cell is served by a first network device; and transmitting a BFRQ to a second network device in a second cell, where the BFRQ is used to indicate that a beam failure event has occurred in the first cell, the second cell is served by the second network device, and the second cell is different from the first cell.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 7, 2023
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Yu Yang, Peng Sun
  • Patent number: 11809667
    Abstract: A transparent conductive substrate structure used for a thermoforming process includes a transparent cover plate and a touch sensing layer structure. The transparent cover plate includes a toughening layer on one side thereof. The touch sensing layer structure arranged on one surface of the toughening layer, and includes a first transparent conductive layer, a dielectric layer, a barrier layer, a second transparent conductive layer, and a buffer protective layer. Each transparent conductive layer is directly applied to the transparent cover plate, so that the thickness between the transparent conductive layers is below 1 ?m. The thickness between layers may be reduced to increase the sensitivity of the touch sensing layer structure. To prevent each transparent conductive layer and an electrode wire layer from breaking during the thermoforming process, the transparent conductive substrate structure is combined with the buffer protective layer to strengthen the structure of each transparent conductive layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 7, 2023
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Sheng-Chieh Tsai, Yao-Zong Chen, Yu-Yang Chang, Hsiou-Ming Liu
  • Publication number: 20230352574
    Abstract: A semiconductor component is provided in the form of an enhancement mode high-electron-mobility transistor having an n-i-p semiconductor junction epitaxial structure. The semiconductor component includes: a channel layer and a barrier layer formed on the channel layer. A two-dimensional electron gas (2DEG) is formed in the channel layer adjacent to an interface between the channel layer and the barrier layer. A gate electrode is disposed on the barrier layer. A semiconductor junction structure is disposed and sandwiched between the gate electrode and the barrier layer. The semiconductor junction structure includes a first region doped with a first dopant and in direct contact with the gate electrode, a second region doped with a second dopant different from the first dopant, and a third region being unintentionally doped and sandwiched between the first region and the second region. The semiconductor junction structure depletes a portion of the 2DEG thereunder.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Shang-Ju Tu, Tien Ching Feng, Chia-Cheng Liu, Ming-Chin Chen, Yu-Jen Liu, Chung-Chih Tsai, Tsung-Cheng Chang, Ya-Yu Yang
  • Publication number: 20230354423
    Abstract: A method of operating a wireless communication device comprises identifying a first start position for performing uplink (UL) transmission in unlicensed spectrum during a first transmission time interval, performing UL transmission in the first transmission time interval (TTI) according to the first start position, identifying a second start position for performing UL transmission in unlicensed spectrum during a second TTI, wherein the first and second start positions correspond to different symbol offsets within the respective first and second TTIs, and performing UL transmission in the second TTI according to the second start position.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 2, 2023
    Inventors: Yu Yang, Reem Karaki, Havish Koorapaty, Jung-Fu Cheng, Sorour Falahati
  • Patent number: 11803709
    Abstract: A method, computer program product and computer system to provide topic guide during document drafting is provided. A processor retrieves at least one section of text from a document. A processor receives a target topic for the document. A processor extracts at least one local topic from the at least one section of text. A processor generates a semantic network comprising the at least one local topic and the target topic. A processor determines a deviation value for the at least one local topic based on a distance between the at least one local topic and the target topic in the semantic network. A processor, in response to the deviation value exceeding a threshold value, alerts a user that the at least one section of text from the document is off-topic from the target topic.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: October 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Xiang Yu Yang, Wen Jie Hao, Zhong Fang Yuan, Wang Hu Dang, Deng Xin Luo, Jia Yong Xie, Wen Wang