Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract: A voltage-stacked system includes a first voltage source, at least one second voltage source, a master monitoring circuit and at least one slave monitoring circuit. The first voltage source and the at least one second voltage source are coupled in series. The master monitoring circuit is coupled to the first voltage source, and arranged for monitoring and controlling the first voltage source and transmitting a monitoring signal. The at least one slave monitoring circuit is respectively coupled to the at least one second voltage source and the master monitoring circuit for monitoring and controlling the at least one second voltage source, and accordingly sending a response signal to the master monitoring circuit.

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.

Abstract: A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles.

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

Abstract: A cutting tool includes a pipe, a pressing foot assembly, a spring, and a blade assembly. The pressing foot assembly is slidably sheathed on an end of the pipe. The spring is sheathed on the pipe. An end of the spring abuts against the pipe, and the other end of the spring abuts against the pressing foot assembly. The blade assembly passes through the pipe and the pressing foot assembly in a slidable manner. When the cutting tool moves along a first direction, the pressing foot assembly keeps pressing against an object in a second direction substantially perpendicular to the first direction, such that the blade assembly protrudes from the pressing foot assembly and cuts the object along the first direction.

Abstract: A method for searching the top-K simple shortest paths between a specified source node and a specified target node in a graph, with graph data partitioned and distributed across a plurality of computing servers, the method including a parallel path search initialized from either one or both of the source and target nodes and traversing the graph by building likely path sequences for a match. Each computing server determines and forwards a path sequence as discovery progresses until the top-K paths are discovered.

Abstract: Large graph data in many application domains dynamically changes with vertices and edges inserted and deleted over time. The problem of identifying and maintaining densely connected regions in the graph thus becomes a challenge. Embodiments of the invention describe a method using a k-core measure as a metric of dense connectivity over large, partitioned graph data stored in multiple computing servers in a cluster. The method describes steps to identify a k-core subgraph in parallel and to maintain a k-core subgraph when a new edge is inserted or an existing edge is deleted. The embodiments thus enable practitioners to identify and monitor large scale graph data, such as exemplified by multiple topical communities in a social network, in a scalable and efficient manner.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole.

Abstract: A method for searching the top-K simple shortest paths between a specified source node and a specified target node in a graph, with graph data partitioned and distributed across a plurality of computing servers, the method including a parallel path search initialized from either one or both of the source and target nodes and traversing the graph by building likely path sequences for a match. Each computing server determines and forwards a path sequence as discovery progresses until the top-K paths are discovered.

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.

Abstract: A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.