Patents by Inventor Yuan-Chih Hsieh

Yuan-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255062
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: November 14, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 12221337
    Abstract: The present disclosure provides a structure and method of fabricating the structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • Patent number: 12185631
    Abstract: In some embodiments, the present disclosure relates to a piezomicroelectromechanical system (piezoMEMS) device that includes a second piezoelectric layer arranged over the first electrode layer. A second electrode layer is arranged over the second piezoelectric layer. A first contact is arranged over and extends through the second electrode layer and the second piezoelectric layer to contact the first electrode layer. A dielectric liner layer is arranged directly between the first contact and inner sidewalls of the second electrode layer and the second piezoelectric layer. A second contact is arranged over and electrically coupled to the second electrode layer, wherein the second contact is electrically isolated from the first contact.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ren Wang, Hung-Hua Lin, Yuan-Chih Hsieh
  • Patent number: 12151932
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Patent number: 12139399
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hua Lin, Chia-Ming Hung, Xin-Hua Huang, Yuan-Chih Hsieh
  • Publication number: 20240368746
    Abstract: A microstructure may be provided by forming a metal layer such as a molybdenum layer over a substrate. An aluminum nitride layer is formed on a top surface of the metal layer. A surface portion of the aluminum nitride layer is converted into a continuous aluminum oxide-containing layer by oxidation. A dielectric spacer layer may be formed over the continuous aluminum oxide-containing layer. Contact via cavities extending through the dielectric spacer layer, the continuous aluminum oxide containing layer, and the aluminum nitride layer and down to a respective portion of the at least one metal layer may be formed using etch processes that contain a wet etch step while suppressing formation of an undercut in the aluminum nitride layer. Contact via structures may be formed in the contact via cavities. The microstructure may include a micro-electromechanical system (MEMS) device containing a piezoelectric transducer.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 7, 2024
    Inventors: Yuan-Chih Hsieh, Yi-Ren Wang, Hung-Hua Lin
  • Publication number: 20240367965
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure overlying a first substrate. A second substrate overlies the dielectric structure and comprises a movable element. A first bond structure is arranged between the dielectric structure and the second substrate. A second bond structure is arranged between the dielectric structure and the second substrate. At least a portion of the movable element is spaced laterally between sidewalls of the second bond structure. The first bond structure comprises a first material and the second bond structure comprises a second material different form the first material. A thickness of the first bond structure is less than a thickness of the second bond structure.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Hung-Hua Lin, Chia-Ming Hung, Xin-Hua Huang, Yuan-Chih Hsieh
  • Patent number: 12134824
    Abstract: A microstructure may be provided by forming a metal layer such as a molybdenum layer over a substrate. An aluminum nitride layer is formed on a top surface of the metal layer. A surface portion of the aluminum nitride layer is converted into a continuous aluminum oxide-containing layer by oxidation. A dielectric spacer layer may be formed over the continuous aluminum oxide-containing layer. Contact via cavities extending through the dielectric spacer layer, the continuous aluminum oxide containing layer, and the aluminum nitride layer and down to a respective portion of the at least one metal layer may be formed using etch processes that contain a wet etch step while suppressing formation of an undercut in the aluminum nitride layer. Contact via structures may be formed in the contact via cavities. The microstructure may include a micro-electromechanical system (MEMS) device containing a piezoelectric transducer.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yuan-Chih Hsieh, Yi-Ren Wang, Hung-Hua Lin
  • Publication number: 20240087879
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11854795
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20230382712
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 30, 2023
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Publication number: 20230371383
    Abstract: In some embodiments, the present disclosure relates to a piezomicroelectromechanical system (piezoMEMS) device that includes a second piezoelectric layer arranged over the first electrode layer. A second electrode layer is arranged over the second piezoelectric layer. A first contact is arranged over and extends through the second electrode layer and the second piezoelectric layer to contact the first electrode layer. A dielectric liner layer is arranged directly between the first contact and inner sidewalls of the second electrode layer and the second piezoelectric layer. A second contact is arranged over and electrically coupled to the second electrode layer, wherein the second contact is electrically isolated from the first contact.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 16, 2023
    Inventors: Yi-Ren Wang, Hung-Hua Lin, Yuan-Chih Hsieh
  • Publication number: 20230365395
    Abstract: The present disclosure provides a structure and method of fabricating the structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • Patent number: 11814283
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Publication number: 20230357002
    Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Inventors: Chih-Ming Chen, Yuan-Chih Hsieh, Chung-Yi Yu
  • Patent number: 11812664
    Abstract: In some embodiments, the present disclosure relates to a piezomicroelectromechanical system (piezoMEMS) device that includes a second piezoelectric layer arranged over the first electrode layer. A second electrode layer is arranged over the second piezoelectric layer. A first contact is arranged over and extends through the second electrode layer and the second piezoelectric layer to contact the first electrode layer. A dielectric liner layer is arranged directly between the first contact and inner sidewalls of the second electrode layer and the second piezoelectric layer. A second contact is arranged over and electrically coupled to the second electrode layer, wherein the second contact is electrically isolated from the first contact.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ren Wang, Hung-Hua Lin, Yuan-Chih Hsieh
  • Patent number: 11767216
    Abstract: The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • Publication number: 20230294978
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a microelectromechanical systems (MEMS) structure overlying a substrate. A capping structure overlies the MEMS structure. The capping structure at least partially defines a cavity. The MEMS structure is disposed in the cavity. An outgas structure adjacent to the cavity. The outgas structure comprises an amorphous material.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Yi-Ren Wang, Shing-Chyang Pan, Yuan-Chih Hsieh
  • Publication number: 20230249961
    Abstract: The present disclosure provides a micro electro mechanical system (MEMS) structure, including a device substrate having a first region and a second region different from the first region, a capping substrate bonded over the device substrate, a first cavity in the first region and between the device substrate and capping substrate, wherein the first cavity has a first cavity pressure, a second cavity in the second region and between the device substrate and capping substrate, wherein the second cavity has a second cavity pressure lower than the first cavity pressure, an outgassing material, wherein the outgassing material includes a top surface and a sidewall exposed to the first cavity, the outgassing material is free from being in direct contact with the capping substrate, wherein the outgassing material includes a trench, and a passivation layer disposed over the device substrate, and is in direct contact with the outgassing material.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventors: YUAN-CHIH HSIEH, HUNG-HUA LIN
  • Patent number: 11713241
    Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Ming Chen, Yuan-Chih Hsieh, Chung-Yi Yu