Patents by Inventor Yuan-Chih Hsieh

Yuan-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10160638
    Abstract: A semiconductor structure may include a first device having first surface with a first bonding layer formed thereon and a second device having a first surface with a second bonding layer formed thereon. The first bonding layer may provide an electrically conductive path to at least one electrical device in the first device. The second bonding layer may provide an electrically conductive path to at least one electrical device in the second device. One of the first or the second devices may include MEMS electrical devices. The first and/or the second bonding layers may be formed of a getter material, which may provide absorption for outgassing.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Cheng Chu, Ping-Yin Liu, Xin-Hua Huang, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng
  • Patent number: 10138118
    Abstract: An integrated circuit (IC) device is provided. The IC device includes a first die including a first substrate and a second die including a second substrate. A plasma-reflecting layer is included on an upper surface of the first die. The plasma-reflecting layer is configured to reflect a plasma therefrom. The second substrate is bonded to the first die so as to form a cavity, wherein a lower surface of the cavity is lined by the plasma-reflecting layer. A dielectric protection layer is present on a lower surface of the second die and lines the upper surface of the cavity. A material of the second substrate has a first etch rate for the plasma and a material of the dielectric protection layer has a second etch rate for the plasma. The second etch rate is less than the first etch rate.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Yen Chou, Chih-Jen Chan, Chia-Shiung Tsai, Ru-Liang Lee, Yuan-Chih Hsieh
  • Patent number: 10119909
    Abstract: A biological sensing structure includes a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to the top surface. The biological sensing structure includes a first light reflecting layer over the top surface and the sidewall surface of the mesa. The biological sensing structure includes a filling material surrounding the mesa, wherein the mesa protrudes from the filling material. The biological sensing structure includes a stop layer over the filling material and a portion of the first light reflecting layer. The biological sensing structure includes a second light reflecting layer over a portion of the stop layer and a portion of the top surface of the mesa. The biological sensing structure includes an opening in the second light reflecting layer to partially expose the top surface of the mesa.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hua Lin, Li-Cheng Chu, Ming-Tung Wu, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 10053361
    Abstract: A microelectromechanical systems (MEMS) package includes a eutectic bonding structure free of a native oxide layer and an anti-stiction layer, while also including a MEMS device having a top surface and sidewalls lined with the anti-stiction layer. The MEMS device is arranged within a MEMS substrate having a first eutectic bonding substructure arranged thereon. A cap substrate having a second eutectic bonding substructure arranged thereon is eutectically bonded to the MEMS substrate with a eutectic bond at the interface of the first and second eutectic bonding substructures. The anti-stiction layer lines a top surface and sidewalls of the MEMS device, but not the first and second eutectic bonding substructures. A method for manufacturing the MEMS package and a process system for selective plasma treatment are also provided.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Hung-Hua Lin, Wen-Chuan Tai, Hsiang-Fu Chen
  • Patent number: 9975757
    Abstract: A microelectromechanical systems (MEMS) structure with a cavity hermetically sealed using a mask layer is provided. A capping substrate is arranged over a MEMS substrate, which includes a movable element. The capping substrate includes the cavity arranged over and opening to the movable element, and includes a seal opening in fluid communication with the cavity. The mask layer is arranged over the capping substrate. The mask layer overhangs the seal opening and laterally surrounds a mask opening arranged over the seal opening. A seal layer is arranged over the mask layer and the mask opening. The seal layer is configured to hermetically seal the cavity. A method for manufacturing the MEMS structure is also provided.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lee-Chuan Tseng, Chung-Yen Chou, Shih-Chang Liu, Yuan-Chih Hsieh
  • Publication number: 20180134542
    Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 17, 2018
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu, Shih-Chang Liu, Yuan-Chih Hsieh
  • Publication number: 20180099865
    Abstract: The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. The structure also includes a movable membrane in the cavity. Further, the structure includes a mesa in the cavity and the mesa is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the mesa, wherein the dielectric layer includes a first surface in contact with the mesa and a second surface opposite to the first surface is positioned toward the cavity.
    Type: Application
    Filed: November 21, 2017
    Publication date: April 12, 2018
    Inventors: Yuan-Chih HSIEH, Hsing-Lien LIN, Jung-Huei PENG, Yi-Chien WU
  • Patent number: 9878899
    Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu, Shih-Chang Liu, Yuan-Chih Hsieh
  • Publication number: 20180022602
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
  • Patent number: 9873610
    Abstract: A MEMS device is described. The device includes a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, a semiconductor substrate including a second bonding layer, and a cap including a third bonding layer, the cap coupled to the semiconductor substrate by bonding the second bonding layer to the third bonding layer. The first bonding layer includes silicon, the semiconductor substrate is electrically coupled to the MEMS substrate by bonding the first bonding layer to the second bonding layer, and the MEMS substrate is hermetically sealed between the cap and the semiconductor substrate.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Hsien Lin, Chia-Hua Chu, Li-Cheng Chu, Yuan-Chih Hsieh, Chun-Wen Cheng
  • Publication number: 20170355598
    Abstract: An integrated circuit (IC) device is provided. The IC device includes a first die including a first substrate and a second die including a second substrate. A plasma-reflecting layer is included on an upper surface of the first die. The plasma-reflecting layer is configured to reflect a plasma therefrom. The second substrate is bonded to the first die so as to form a cavity, wherein a lower surface of the cavity is lined by the plasma-reflecting layer. A dielectric protection layer is present on a lower surface of the second die and lines the upper surface of the cavity. A material of the second substrate has a first etch rate for the plasma and a material of the dielectric protection layer has a second etch rate for the plasma. The second etch rate is less than the first etch rate.
    Type: Application
    Filed: August 8, 2017
    Publication date: December 14, 2017
    Inventors: Chung-Yen Chou, Chih-Jen Chan, Chia-Shiung Tsai, Ru-Liang Lee, Yuan-Chih Hsieh
  • Patent number: 9828234
    Abstract: The present disclosure provides a method of manufacturing a structure. The method comprises: providing a first substrate; forming a plurality of conductive pads over the first substrate; forming a film on a first subset of the plurality of conductive pads, thereby leaving a second subset of the plurality of conductive pads exposed from the film; forming a self-assembled monolayer (SAM) over the film; and forming a cavity by the first substrate and a second substrate through bonding a portion of the second substrate to the second subset of the plurality of conductive pads that are exposed from the film.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • Publication number: 20170313581
    Abstract: A method of making a micro electromechanical system (MEMS) package includes patterning a substrate to form a MEMS section. The method further includes bonding a carrier to a surface of the substrate. The carrier is free of active devices. The carrier includes a carrier bond pad on a surface of the carrier opposite the MEMS section. The carrier bond pad is electrically connected to the MEMS section. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad. The bonding of the wafer bond pad to the carrier bond pad includes re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
    Type: Application
    Filed: July 7, 2017
    Publication date: November 2, 2017
    Inventors: Chun-wen CHENG, Hung-Chia TSAI, Lan-Lin CHAO, Yuan-Chih HSIEH, Ping-Yin LIU
  • Publication number: 20170313574
    Abstract: The present disclosure provides a method of manufacturing a structure. The method comprises: providing a first substrate; forming a plurality of conductive pads over the first substrate; forming a film on a first subset of the plurality of conductive pads, thereby leaving a second subset of the plurality of conductive pads exposed from the film; forming a self-assembled monolayer (SAM) over the film; and forming a cavity by the first substrate and a second substrate through bonding a portion of the second substrate to the second subset of the plurality of conductive pads that are exposed from the film.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventors: YUAN-CHIH HSIEH, HSING-LIEN LIN, JUNG-HUEI PENG, YI-CHIEN WU
  • Patent number: 9796584
    Abstract: A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Ming Chang, Chih-Jen Chan, Chung-Yen Chou, Lee-Chuan Tseng, Shih-Wei Lin, Yuan-Chih Hsieh
  • Patent number: 9776858
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
  • Patent number: 9776852
    Abstract: The present disclosure provides a method for manufacturing a CMOS-MEMS structure. The method includes etching a cavity on a first surface of a cap substrate; bonding the first surface of the cap substrate with a sensing substrate; thinning a second surface of the sensing substrate, the second surface being opposite to a third surface of the sensing substrate bonded to the cap substrate; etching the second surface of the sensing substrate; patterning a portion of the second surface of the sensing substrate to form a plurality of bonding regions; depositing an eutectic metal layer on the plurality of bonding regions; etching a portion of the sensing substrate under the cavity to form a movable element; and bonding the sensing substrate to a CMOS substrate through the eutectic metal layer.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yuan-Chih Hsieh, Lee-Chuan Tseng, Hung-Hua Lin
  • Patent number: 9738516
    Abstract: A method of forming an IC (integrated circuit) device is provided. The method includes receiving a first wafer including a first substrate and including a plasma-reflecting layer disposed on an upper surface thereof. The plasma-reflecting layer is configured to reflect a plasma therefrom. A dielectric protection layer is formed on a lower surface of a second wafer, wherein the second wafer includes a second substrate. The second wafer is bonded to the first wafer, such that a cavity is formed between the plasma-reflecting layer and the dielectric protection layer. An etch process is performed with the plasma to form an opening extending from an upper surface of the second wafer and through the dielectric protection layer into the cavity. A resulting structure of the above method is also provided.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Yen Chou, Chih-Jen Chan, Chia-Shiung Tsai, Ru-Liang Lee, Yuan-Chih Hsieh
  • Publication number: 20170225947
    Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
    Type: Application
    Filed: April 1, 2016
    Publication date: August 10, 2017
    Inventors: CHIH-MING CHEN, YUAN-CHIH HSIEH, CHUNG-YI YU
  • Patent number: 9725310
    Abstract: A micro electromechanical system (MEMS) device includes a MEMS section attached to a substrate, and a cap bonded to a first surface of the substrate. The MEMS device further includes a carrier bonded to a second surface of the substrate opposite the first surface, wherein the carrier is free of active devices, and the cap and the carrier define a vacuum region surrounding the MEMS section. The MEMS device further includes a bond pad on a surface of the carrier opposite the MEMS section, wherein the bond pad is electrically connected to the MEMS section.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-wen Cheng, Hung-Chia Tsai, Lan-Lin Chao, Yuan-Chih Hsieh, Ping-Yin Liu