Patents by Inventor Yuan-Chih Hsieh

Yuan-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR CONTROLLING SURFACE ROUGHNESS IN MEMS STRUCTURE
    Publication number: 20170217756
    Abstract: The present disclosure provides a method for manufacturing a CMOS-MEMS structure. The method includes etching a cavity on a first surface of a cap substrate; bonding the first surface of the cap substrate with a sensing substrate; thinning a second surface of the sensing substrate, the second surface being opposite to a third surface of the sensing substrate bonded to the cap substrate; etching the second surface of the sensing substrate; patterning a portion of the second surface of the sensing substrate to form a plurality of bonding regions; depositing an eutectic metal layer on the plurality of bonding regions; etching a portion of the sensing substrate under the cavity to form a movable element; and bonding the sensing substrate to a CMOS substrate through the eutectic metal layer.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 3, 2017
    Inventors: YUAN-CHIH HSIEH, LEE-CHUAN TSENG, HUNG-HUA LIN
  • CMOS compatible biofet
    Patent number: 9714914
    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with a sensing well having one or more sensing well spacers that reduce a size of the sensing well after its formation. In some embodiments, the integrated bio-sensor has a sensing device disposed within a semiconductor substrate. A dielectric structure is disposed onto a first side of the semiconductor substrate. The dielectric structure has an opening with a first width, which is exposed to an ambient environment and that overlies the sensing device. One or more sensing well spacers are arranged on sidewalls of the opening. The one or more sensing well spacers expose a bottom surface of the opening to define a sensing well having a second width that is smaller than the first width.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lee-Chuan Tseng, Che-Ming Chang, Chung-Yen Chou, Yuan-Chih Hsieh
  • Method of improving getter efficiency by increasing superficial area
    Patent number: 9708179
    Abstract: In some embodiments, the present disclosure relates to a MEMs (microelectromechanical system) package device having a getter layer. The MEMs package includes a first substrate having a cavity located within an upper surface of the first substrate. The cavity has roughened interior surfaces. A getter layer is arranged onto the roughened interior surfaces of the cavity. A bonding layer is arranged on the upper surface of the first substrate on opposing sides of the cavity, and a second substrate bonded to the first substrate by the bonding layer. The second substrate is arranged over the cavity. The roughened interior surfaces of the cavity enables more effective absorption of residual gases, thereby increasing the efficiency of a gettering process.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Hung-Hua Lin, Chih-Jen Chan, Lan-Lin Chao
  • METHOD FOR FABRICATING A MICRO-WELL OF A BIOSENSOR
    Publication number: 20170158500
    Abstract: A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.
    Type: Application
    Filed: February 20, 2017
    Publication date: June 8, 2017
    Inventors: Che-Ming Chang, Chih-Jen Chan, Chung-Yen Chou, Lee-Chuan Tseng, Shih-Wei Lin, Yuan-Chih Hsieh
  • Cup-like getter scheme
    Patent number: 9637378
    Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by increasing an area in which a getter layer is deposited, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having one or more residual gases. A cavity is formed within a top surface of the substrate. The cavity has a bottom surface and sidewalls extending from the bottom surface to the top surface. A getter layer, which absorbs the one or more residual gases, is deposited over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls. By depositing the getter layer to extend to a location on the sidewalls of the cavity, the area of the substrate that is able to absorb the one or more residual gases is increased.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Jen Chan, Lee-Chuan Tseng, Shih-Wei Lin, Che-Ming Chang, Chung-Yen Chou, Yuan-Chih Hsieh
  • METHOD AND APPARATUS FOR REDUCING IN-PROCESS AND IN-USE STICTION FOR MEMS DEVICES
    Publication number: 20170096328
    Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu, Shih-Chang Liu, Yuan-Chih Hsieh
  • Self-removal anti-stiction coating for bonding process
    Patent number: 9611141
    Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Li-Cheng Chu, Hung-Hua Lin, Shang-Ying Tsai, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Method for fabricating a micro-well of a biosensor
    Patent number: 9606081
    Abstract: A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Ming Chang, Chih-Jen Chan, Chung-Yen Chou, Lee-Chuan Tseng, Shih-Wei Lin, Yuan-Chih Hsieh
  • Integrate Rinse Module in Hybrid Bonding Platform
    Publication number: 20170004964
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • MEMS structures and methods for forming the same
    Patent number: 9533876
    Abstract: A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Hsin-Ting Huang, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Grinding wheel for wafer edge trimming
    Patent number: 9527188
    Abstract: A grinding wheel for wafer edge trimming includes a head having an open side and an abrasive end bonded around an edge of the open side of the head. The abrasive end is arranged to have multiple simultaneous contacts around a wafer edge during the wafer edge trimming.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • WAFER LEVEL HERMETIC SEAL PROCESS FOR MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICES
    Publication number: 20160355394
    Abstract: A microelectromechanical systems (MEMS) structure with a cavity hermetically sealed using a mask layer is provided. A capping substrate is arranged over a MEMS substrate, which includes a movable element. The capping substrate includes the cavity arranged over and opening to the movable element, and includes a seal opening in fluid communication with the cavity. The mask layer is arranged over the capping substrate. The mask layer overhangs the seal opening and laterally surrounds a mask opening arranged over the seal opening. A seal layer is arranged over the mask layer and the mask opening. The seal layer is configured to hermetically seal the cavity. A method for manufacturing the MEMS structure is also provided.
    Type: Application
    Filed: June 3, 2015
    Publication date: December 8, 2016
    Inventors: Lee-Chuan Tseng, Chung-Yen Chou, Shih-Chang Liu, Yuan-Chih Hsieh
  • STRUCTURE TO REDUCE BACKSIDE SILICON DAMAGE
    Publication number: 20160318757
    Abstract: A method of forming an IC (integrated circuit) device is provided. The method includes receiving a first wafer including a first substrate and including a plasma-reflecting layer disposed on an upper surface thereof. The plasma-reflecting layer is configured to reflect a plasma therefrom. A dielectric protection layer is formed on a lower surface of a second wafer, wherein the second wafer includes a second substrate. The second wafer is bonded to the first wafer, such that a cavity is formed between the plasma-reflecting layer and the dielectric protection layer. An etch process is performed with the plasma to form an opening extending from an upper surface of the second wafer and through the dielectric protection layer into the cavity. A resulting structure of the above method is also provided.
    Type: Application
    Filed: April 29, 2015
    Publication date: November 3, 2016
    Inventors: Chung-Yen Chou, Chih-Jen Chan, Chia-Shiung Tsai, Ru-Liang Lee, Yuan-Chih Hsieh
  • Semiconductor having a high aspect ratio via
    Patent number: 9472504
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: October 18, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Ming-Tung Wu, Ping-Yin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Biological Sensing Structures
    Publication number: 20160299068
    Abstract: A biological sensing structure includes a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to the top surface. The biological sensing structure includes a first light reflecting layer over the top surface and the sidewall surface of the mesa. The biological sensing structure includes a filling material surrounding the mesa, wherein the mesa protrudes from the filling material. The biological sensing structure includes a stop layer over the filling material and a portion of the first light reflecting layer. The biological sensing structure includes a second light reflecting layer over a portion of the stop layer and a portion of the top surface of the mesa. The biological sensing structure includes an opening in the second light reflecting layer to partially expose the top surface of the mesa.
    Type: Application
    Filed: June 23, 2016
    Publication date: October 13, 2016
    Inventors: Hung-Hua Lin, Li-Cheng Chu, Ming-Tung Wu, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Integrate rinse module in hybrid bonding platform
    Patent number: 9446467
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Xin-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • METHOD FOR FABRICATING A MICRO-WELL OF A BIOSENSOR
    Publication number: 20160266063
    Abstract: A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 15, 2016
    Inventors: Che-Ming Chang, Chih-Jen Chan, Chung-Yen Chou, Lee-Chuan Tseng, Shih-Wei Lin, Yuan-Chih Hsieh
  • Robot blade design
    Patent number: 9434076
    Abstract: The present disclosure relates to a wafer transfer robot having a robot blade that can be used to handle substrates that are patterned on both sides without causing warpage of the substrates. In some embodiments, the wafer transfer robot has a robot blade coupled to a transfer arm that varies a position of the robot blade. The robot blade has a wafer reception area that receives a substrate. Two or more spatially distinct contact points are located at positions along a perimeter of the wafer reception area that provide support to opposing edges of the substrate. The two or more contact points are separated by a cavity in the robot blade. The cavity mitigates contact between a backside of the substrate and the robot blade, while providing support to opposing sides of the substrate to prevent warpage of the substrate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lee-Chuan Tseng, Chih-Jen Chan, Shih-Wei Lin, Che-Ming Chang, Chung-Yen Chou, Yuan-Chih Hsieh
  • SELF-REMOVAL ANTI-STICTION COATING FOR BONDING PROCESS
    Publication number: 20160229693
    Abstract: A bond free of an anti-stiction layer and bonding method is disclosed. An exemplary method includes forming a first bonding layer; forming an interlayer over the first bonding layer; forming an anti-stiction layer over the interlayer; and forming a liquid from the first bonding layer and interlayer, such that the anti-stiction layer floats over the first bonding layer. A second bonding layer can be bonded to the first bonding layer while the anti-stiction layer floats over the first bonding layer, such that a bond between the first and second bonding layers is free of the anti-stiction layer.
    Type: Application
    Filed: December 9, 2014
    Publication date: August 11, 2016
    Inventors: Ping-Yin Liu, Li-Cheng Chu, Hung-Hua Lin, Shang-Ying Tsai, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • CMOS COMPATIBLE BIOFET
    Publication number: 20160209355
    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with a sensing well having one or more sensing well spacers that reduce a size of the sensing well after its formation. In some embodiments, the integrated bio-sensor has a sensing device disposed within a semiconductor substrate. A dielectric structure is disposed onto a first side of the semiconductor substrate. The dielectric structure has an opening with a first width, which is exposed to an ambient environment and that overlies the sensing device. One or more sensing well spacers are arranged on sidewalls of the opening. The one or more sensing well spacers expose a bottom surface of the opening to define a sensing well having a second width that is smaller than the first width.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 21, 2016
    Inventors: Lee-Chuan Tseng, Che-Ming Chang, Chung-Yen Chou, Yuan-Chih Hsieh