Patents by Inventor Yuan FU

Yuan FU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11024603
    Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 1, 2021
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
  • Publication number: 20210151321
    Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.
    Type: Application
    Filed: December 29, 2020
    Publication date: May 20, 2021
    Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
  • Patent number: 10964742
    Abstract: A circuit that includes: a photodiode configured to absorb photons and to generate photo-carriers from the absorbed photons; a first MOSFET transistor that includes: a first channel terminal coupled to a first terminal of the photodiode and configured to collect a portion of the photo-carriers generated by the photodiode; a second channel terminal; and a gate terminal coupled to a first control voltage source; a first readout circuit configured to output a first readout voltage; a second readout circuit configured to output a second readout voltage; and a current-steering circuit configured to steer the photo-carriers generated by the photodiode to one or both of the first readout circuit and the second readout circuit.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: March 30, 2021
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang, Yuan-Fu Lyu, Chien-Lung Chen, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 10916427
    Abstract: The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
  • Publication number: 20210015890
    Abstract: The present disclosure provides compositions comprising Ganoderma immunomodulatory protein or a recombinant thereof and a gel-forming agent. Also provided are methods for the treatment of chronic wounds, ulcers or sores, and methods using the compositions.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventors: HSU-YUAN FU, YU-CHE CHENG
  • Publication number: 20210018848
    Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Inventors: Ta-Ching YU, Shih-Che WANG, Shu-Hao CHANG, Yi-Hao CHEN, Chen-Yen KAO, Te-Chih HUANG, Yuan-Fu HSU
  • Patent number: 10892250
    Abstract: A stacked package structure has a metal casing, a stacked chipset, an encapsulation and a redistribution layer. The stacked chipset is adhered in the metal casing. The encapsulation is formed in the metal casing to encapsulate the stacked chip set, but a plurality of surfaces of the metal pads are exposed through the encapsulation. The redistribution layer is further formed on the encapsulation and electrically connects to the metal pads of the stacked chipset. Therefore, the stacked package structure includes the metal casing, so an efficiency of heat dissipation and structural strength are increased.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 12, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Hsien-Wen Hsu
  • Publication number: 20200408757
    Abstract: Disclosed herein is a T-helper cell (“TH-GM” cell) that is regulated by IL-7/STAT5 and which secrete GM-CSF/IL-3. Also disclosed are methods and compositions for modulating TH-GM function for the treatment of, e.g., inflammatory disorders. Diagnostic and prognostic methods for specifically identifying TH-GM-mediated inflammatory disorders (e.g., rheumatoid arthritis), as distinct from and/or in addition to non-TH-GM-mediated (e.g., TNF-?-mediated) inflammatory disorders, are also provided.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 31, 2020
    Applicant: National University of Singapore
    Inventors: Xin-yuan FU, Wanqiang SHENG, Yongliang ZHANG, Fan YANG
  • Publication number: 20200402837
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.
    Type: Application
    Filed: July 22, 2019
    Publication date: December 24, 2020
    Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
  • Patent number: 10867899
    Abstract: A method of manufacturing a semiconductor package includes: (1) providing a first passivation layer on a carrier; (2) patterning the first passivation layer to define a first hole; (3) disposing a first seed layer on the first hole; (4) disposing a first conductive layer on the first seed layer; (5) replacing the carrier with a second passivation layer; (6) patterning the second passivation layer to define a second hole exposing the first seed layer; and (7) disposing a second conductive layer on the exposed first seed layer through the second hole.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: December 15, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Fu Sung, Shin-Hua Chao, Ming-Chi Liu, Hung-Sheng Chen
  • Patent number: 10861888
    Abstract: An optical apparatus that includes: a semiconductor substrate formed from a first material, the semiconductor substrate including a first n-doped region; and a photodiode supported by the semiconductor substrate, the photodiode including an absorption region configured to absorb photons and to generate photo-carriers from the absorbed photons, the absorption region being formed from a second material different than the first material and including: a first p-doped region; and a second n-doped region coupled to the first n-doped region, wherein a second doping concentration of the second n-doped region is less than or substantially equal to a first doping concentration of the first n-doped region.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 8, 2020
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang, Yuan-Fu Lyu, Chien-Lung Chen, Chung-Chih Lin, Kuan-Chen Chu
  • Publication number: 20200373267
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 10795270
    Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Ching Yu, Shih-Che Wang, Shu-Hao Chang, Yi-Hao Chen, Chen-Yen Kao, Te-Chih Huang, Yuan-Fu Hsu
  • Publication number: 20200306235
    Abstract: Disclosed are methods and compositions for treating ore preventing a STAT5-mediated medical condition, e.g., rheumatoid arthritis, in a subject by administering to the subject a therapeutically effective amount of a compound, the compound being a STAT5 inhibitor, or a pharmaceutically acceptable salt of the STAT5 inhibitor, or a solvate of the STAT5 inhibitor, or a prodrug of the STAT5 inhibitor. In one example, the compound used in the methods and compositions is pimozide. In another example, the compound used in the methods and compositions is nicotinohydrazide.
    Type: Application
    Filed: May 4, 2018
    Publication date: October 1, 2020
    Applicant: Generos Biopharma Ltd.
    Inventor: Xin-Yuan Fu
  • Patent number: 10784189
    Abstract: A mounting rack with circuit includes a leadframe, a molding seat and a circuit layer. The leadframe comprises a plurality of electrodes. The molding seat is arranged on the leadframe and has a cup body to expose backsides of the electrodes and a cup opening to expose front sides of the electrodes. The circuit layer is arranged on the cup body and at least comprises two conductive parts, two electrical-connection parts and two soldering pads, wherein the two electrical-connection parts are arranged on the cup opening, one end of each of the two electrical-connection parts is electrically connected to one end of a respective one of the two conductive parts, the two soldering pads are arranged on bottom of the cup body, each of the two soldering pads is electrically connected to the other end of a respective one of the two conductive parts.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 22, 2020
    Assignee: FUSHENG ELECTRONICS CORPORATION
    Inventors: Chen-Feng Chu, Yuan-Fu Chen
  • Publication number: 20200278782
    Abstract: The driving apparatus for driving a touch display panel includes a first voltage generating circuit configured to generate a common reference voltage, a second voltage generating circuit configured to generate a touch driving signal, and a control circuit configured to generate a switching signal. The switching signal is at the first voltage level during display periods for providing the common reference voltage to the touch display panel. The switching signal is at the second voltage level during touch periods for providing the touch driving signal to the touch display panel. A first touch display period includes a first display period a first touch period adjacent to the first display period. A second touch display period includes a second display period and a second touch period adjacent to the second display period. The first touch display period and the second touch display period are different in time length.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Feng-Lin CHAN, Hung-Kai CHEN, Yuan-Fu HSUEH, Chun-Yuan PAI
  • Patent number: 10749664
    Abstract: An apparatus includes a slicer circuit, a frequency acquisition circuit, a phase acquisition circuit and an oscillator circuit. The slicer circuit may be configured to (i) generate an output signal by slicing a data signal in response to a clock signal and (ii) generate a crossing signal in response to the data signal and the clock signal. The frequency acquisition circuit may be configured to generate a first control signal and a second control signal in response to the data signal and the clock signal. The phase acquisition circuit may be configured to generate a third control signal in response to the first control signal and the data crossing signal. The oscillator circuit may be configured to generate the clock signal in response to the second control signal and the third control signal. The second control signal may shift an adjustable frequency range of the clock signal.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: August 18, 2020
    Assignee: Ambarella International LP
    Inventors: Xuan Wang, Jingxiao Li, Tianwei Liu, Yuan-Fu Lin
  • Patent number: 10741513
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20200222444
    Abstract: The disclosure provides a method of inhibiting proliferation of a cell, inhibiting m3C formation in a cell, inhibiting activity of Mettl8 in a cell, or activating ATM and p53 in a cell, the method comprising contacting the cell with a Mettl8 inhibitor. The disclosure also provides a composition comprising a cell with a reduced expression or activity of Mettl8. In another aspect, the disclosure provides methods of rendering a tumor cell sensitive to a cancer therapy.
    Type: Application
    Filed: July 6, 2018
    Publication date: July 16, 2020
    Applicant: NATIONAL UNIVERSITY OF SINGAPORE
    Inventors: Xin-Yuan FU, Xinyu LIU, Lu Ang XU
  • Patent number: 10707260
    Abstract: A circuit that includes: a photodiode configured to absorb photons and to generate photo-carriers from the absorbed photons; a first MOSFET transistor that includes: a first channel terminal coupled to a first terminal of the photodiode and configured to collect a portion of the photo-carriers generated by the photodiode; a second channel terminal; and a gate terminal coupled to a first control voltage source; a first readout circuit configured to output a first readout voltage; a second readout circuit configured to output a second readout voltage; and a current-steering circuit configured to steer the photo-carriers generated by the photodiode to one or both of the first readout circuit and the second readout circuit.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 7, 2020
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang, Yuan-Fu Lyu, Chien-Lung Chen, Chung-Chih Lin, Kuan-Chen Chu