Patents by Inventor Yuan FU

Yuan FU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10204826
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a trench in the IMD layer; performing a treatment process to transform part of the IMD layer into a damaged layer adjacent to the trench; forming a protective layer on a sidewall of the damaged layer; forming a metal layer in the trench; and removing the damaged layer to form an air gap adjacent to the protective layer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Shiang Hsu, Yuan-Fu Ko, Chih-Sheng Chang
  • Publication number: 20180376388
    Abstract: A wireless communicating method includes: transmitting a querying signal to at least one access point (AP) to request at least one key cache stored in the at least one AP, wherein one of the at least one APs has established a connection with a station; and receiving said at least one key cache from the at least one AP.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 27, 2018
    Inventors: Yuan-Fu Luo, Kuo-Hsuan Lee, Yi-Wei Chung, Hai-Pin Liang, Po-Hsun Yang
  • Patent number: 10163836
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 10141252
    Abstract: A semiconductor package includes: a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole being further defined by a first sidewall and a second sidewall of the passivation layer; a first conductive layer on the first surface of the passivation layer and the first sidewall; a second conductive layer on the second surface of the passivation layer and the second sidewall; and a third conductive layer between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 27, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Fu Sung, Shin-Hua Chao, Ming-Chi Liu, Hung-Sheng Chen
  • Publication number: 20180329570
    Abstract: The driving apparatus for driving a touch display panel includes a first voltage generating circuit configured to generate a common reference voltage, a second voltage generating circuit configured to generate a touch driving signal, and a control circuit configured to generate a switching signal. The switching signal is at the first voltage level during display periods for providing the common reference voltage to the touch display panel. The switching signal is at the second voltage level during touch periods for providing the touch driving signal to the touch display panel. A first touch display period includes a first display period a first touch period adjacent to the first display period. A second touch display period includes a second display period and a second touch period adjacent to the second display period. The first touch display period and the second touch display period are different in time length.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 15, 2018
    Inventors: Feng-Lin CHAN, Hung-Kai CHEN, Yuan-Fu HSUEH, Chun-Yuan PAI
  • Publication number: 20180315674
    Abstract: A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Inventors: Ming-Chih Chen, Hsien-Wen Hsu, Yuan-Fu Lan, Hung-Hsin Hsu
  • Patent number: 10096543
    Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: October 9, 2018
    Assignee: MediaTek Inc.
    Inventors: Chien-Kai Huang, Yuan-Fu Chung, Yuan-Hung Chung
  • Publication number: 20180247968
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 30, 2018
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Publication number: 20180233443
    Abstract: A semiconductor package includes: a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole being further defined by a first sidewall and a second sidewall of the passivation layer; a first conductive layer on the first surface of the passivation layer and the first sidewall; a second conductive layer on the second surface of the passivation layer and the second sidewall; and a third conductive layer between the first conductive layer and the second conductive layer.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 16, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Fu SUNG, Shin-Hua CHAO, Ming-Chi LIU, Hung-Sheng CHEN
  • Publication number: 20180233521
    Abstract: An optical apparatus that includes: a semiconductor substrate formed from a first material, the semiconductor substrate including a first n-doped region; and a photodiode supported by the semiconductor substrate, the photodiode including an absorption region configured to absorb photons and to generate photo-carriers from the absorbed photons, the absorption region being formed from a second material different than the first material and including: a first p-doped region; and a second n-doped region coupled to the first n-doped region, wherein a second doping concentration of the second n-doped region is less than or substantially equal to a first doping concentration of the first n-doped region.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang, Yuan-Fu Lyu, Chien-Lung Chen, Chung-Chih Lin, Kuan-Chen Chu
  • Publication number: 20180233528
    Abstract: A circuit that includes: a photodiode configured to absorb photons and to generate photo-carriers from the absorbed photons; a first MOSFET transistor that includes: a first channel terminal coupled to a first terminal of the photodiode and configured to collect a portion of the photo-carriers generated by the photodiode; a second channel terminal; and a gate terminal coupled to a first control voltage source; a first readout circuit configured to output a first readout voltage; a second readout circuit configured to output a second readout voltage; and a current-steering circuit configured to steer the photo-carriers generated by the photodiode to one or both of the first readout circuit and the second readout circuit.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang, Yuan-Fu Lyu, Chien-Lung Chen, Chung-Chih Lin, Kuan-Chen Chu
  • Publication number: 20180212572
    Abstract: The present invention provides a class AB amplifier, wherein the class AB amplifier includes a cascode stage with a filter and an output stage. The cascode stage with the filter is arranged for receiving an input signal to generate a first driving signal and a second driving signal, wherein the filter filters the input signal to generate an filtered input signal, and at least one of the first driving signal and the second driving signal is generated according to the filtered input signal. The output stage is coupled to the cascode stage, and is arranged for generating an output signal according to the first driving signal and the second driving signal.
    Type: Application
    Filed: December 14, 2017
    Publication date: July 26, 2018
    Inventors: Jui-Yu Hsu, Yuan-Fu Lyu, Sheng-Hao Chen
  • Patent number: 10008794
    Abstract: An operation member for an electronic device is provided. The electronic device includes a casing having portions defining an opening and a circuit module having a circuit board. The circuit board includes a controller. The operation member includes a body including an operating end and a coupling end, and a skirt member. The body is configured to partially protrude through the opening of the casing for operating. The skirt member is arranged at the coupling end. The skirt member includes a base plate outwardly extending from the coupling end, a wall upwardly extending from peripheral portions of the base plate, and a groove defined between the wall and the body. The operation member is configured to associate with the electronic device, and the operation member with the body and the skirt is completely separated from the casing.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 26, 2018
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chun-Lung Ho, Yi-Hsun Lee, Ming-Wei Ou, Yuan-Fu Lin
  • Publication number: 20180166409
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: January 22, 2018
    Publication date: June 14, 2018
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20180142073
    Abstract: A biodecomposable film material includes: a biodecomposable material which is one or more selected from the group consisting of polylactic acid, poly(butylene adipate-co-terephthalate) and poly butylene succinate and which has a mass percentage of 60-70%; a food grade agricultural waste having a diameter smaller than 50 ?m and a mass percentage of 10-30%; a modifier which is calcium carbonate powder or magnesium silicate salt powder and which has a diameter smaller than 8 ?m and a mass percentage of 7-29%; and an organic decomposing bacterium which is Bacillus amyloliquefaciens. The organic decomposing bacterium is heat resistant bacillus capable of withstanding a temperature of 100° C. and has a mass percentage of 1-3%. The biodecomposable material, the food grade agricultural waste, the modifier, and the organic decomposing bacterium are subjected to compounding and blowing to form a film having a thickness of 40-60 ?m.
    Type: Application
    Filed: November 23, 2017
    Publication date: May 24, 2018
    Inventors: Sheng-Yen Wu, Feng-Chia Hsieh, Yuan-Fu Jhong, Yao-Kuei Hsiao
  • Publication number: 20180114782
    Abstract: A manufacturing method of a package-on package structure including at least the following steps is provided. A die is bonded on a first circuit carrier. A spacer is disposed on the die. The spacer and the first circuit carrier are connected through a plurality of conductive wires. An encapsulant is formed to encapsulate the die, the spacer and the conductive wires. A thickness of the encapsulant is reduced until at least a portion of each of the conductive wires is removed to form a first package structure. A second package structure is stacked on the first package structure. The second package structure is electrically connected to the conductive wires.
    Type: Application
    Filed: September 28, 2017
    Publication date: April 26, 2018
    Applicant: Powertech Technology Inc.
    Inventors: Chi-An Wang, Hung-Hsin Hsu, Yuan-Fu Lan, Hsien-Wen Hsu
  • Publication number: 20180041046
    Abstract: A multi-power supply device includes a plurality of power input units configured to each supply an input power and being DC power input units, AC power input units, or a combination thereof; power channel control units electrically connected to the power input units, respectively, and turned on as soon as the output end voltage of the power channel control units is lower than the input end voltage of the power channel control units, wherein the power channel control unit with the highest input voltage is turned on to output an ON voltage; and a power output unit electrically connected to the power channel control units and adapted to output the ON voltage.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 8, 2018
    Inventors: KAI-YUAN FU, RUH-HUA WU, CHUNG-TSENG CHANG
  • Patent number: 9875979
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 9793337
    Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 17, 2017
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
  • Publication number: 20170229442
    Abstract: A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Chien-Kai HUANG, Yuan-Fu CHUNG, Bo-Shih HUANG, Chang-Tzu WANG