Patents by Inventor Yuan FU

Yuan FU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170222343
    Abstract: An operation member for an electronic device is provided. The electronic device includes a casing having portions defining an opening and a circuit module having a circuit board. The circuit board includes a controller. The operation member includes a body including an operating end and a coupling end, and a skirt member. The body is configured to partially protrude through the opening of the casing for operating. The skirt member is arranged at the coupling end. The skirt member includes a base plate outwardly extending from the coupling end, a wall upwardly extending from peripheral portions of the base plate, and a groove defined between the wall and the body. The operation member is configured to associate with the electronic device, and the operation member with the body and the skirt is completely separated from the casing.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: CHUN-LUNG HO, YI-HSUN LEE, MING-WEI OU, YUAN-FU LIN
  • Patent number: 9684330
    Abstract: An operation member includes a body having an operating end and a coupling end, and a skirt member. The skirt member is arranged at the coupling end. The skirt member includes a base plate outwardly extending from the coupling end, a wall extending from the base plate, and a groove defined between the outer surface of the wall and the body. The electronic device includes a casing, an operation member, and a circuit module. The casing has portions defining an opening. The circuit module has a circuit board including a controller disposed thereon. The above-mentioned operation member is sleeved onto the controller and passes through the opening. The outer surface of the operation member and the opening define a gap therebetween. The groove is correspondingly arranged proximate to the gap to gather small particles entering the gap.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: June 20, 2017
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chun-Lung Ho, Yi-Hsun Lee, Ming-Wei Ou, Yuan-Fu Lin
  • Patent number: 9666576
    Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 30, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chien-Kai Huang, Yuan-Fu Chung, Bo-Shih Huang, Chang-Tzu Wang
  • Patent number: 9659884
    Abstract: A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. The first conductive patterns and the first dummy pattern are located in the first layout region. The second conductive patterns and the second dummy pattern are located in the second layout region. The first and second conductive patterns and the first and second dummy patterns are embedded in the insulation encapsulation. The insulation encapsulation exposes top surfaces of the first and second conductive patterns and the first and second dummy patterns. The first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns. An edge profile of the first dummy pattern facing the second dummy pattern is non-linear.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: May 23, 2017
    Assignee: Powertech Technology Inc.
    Inventors: Yuan-Fu Lan, Hsien-Wen Hsu
  • Publication number: 20170141059
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 9627280
    Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Yasutoshi Okuno, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wei-Chun Tsai
  • Publication number: 20170047295
    Abstract: A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. The first conductive patterns and the first dummy pattern are located in the first layout region. The second conductive patterns and the second dummy pattern are located in the second layout region. The first and second conductive patterns and the first and second dummy patterns are embedded in the insulation encapsulation. The insulation encapsulation exposes top surfaces of the first and second conductive patterns and the first and second dummy patterns. The first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns. An edge profile of the first dummy pattern facing the second dummy pattern is non-linear.
    Type: Application
    Filed: October 20, 2016
    Publication date: February 16, 2017
    Applicant: Powertech Technology Inc.
    Inventors: Yuan-Fu Lan, Hsien-Wen Hsu
  • Publication number: 20170047277
    Abstract: Provided is a semiconductor structure including a first die and a second die. The first die has a first conductive structure embedded in a dielectric layer. The second die has a second conductive structure embedded in the dielectric layer. A first interface is provided between the first conductive structure and the dielectric layer. A second interface is provided between the second conductive structure and the dielectric layer. A shape of the dielectric layer between the first interface and the second interface is a non-linear shape.
    Type: Application
    Filed: April 12, 2016
    Publication date: February 16, 2017
    Inventors: Yuan-Fu Lan, Hsien-Wen Hsu
  • Patent number: 9508786
    Abstract: A method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: November 29, 2016
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
  • Patent number: 9455325
    Abstract: An apparatus includes a semiconductor substrate having a plurality of fins, wherein the plurality of fins includes a first group of fins and a second group of fins. The apparatus further includes a high fin density area on the semiconductor substrate including a first dielectric between the first group of fins in the high fin density area, said first dielectric having a first dopant concentration. The apparatus further includes a low fin density area on the semiconductor substrate including a second dielectric between the second group of fins in the low fin density area, said second dielectric having a second dopant concentration. The first dielectric and the second dielectric are a same material as deposited and the first dopant concentration and the second dopant concentration are different.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wen-Huei Guo, Tung Ying Lee
  • Publication number: 20160276338
    Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 22, 2016
    Inventors: Yuan-Fu CHUNG, Chu-Wei HU, Yuan-Hung CHUNG
  • Publication number: 20160268174
    Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Inventors: Clement Hsingjen Wann, Yasutoshi Okuno, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wei-Chun Tsai
  • Patent number: 9444231
    Abstract: A mounting mechanism for gripping DIN rail comprises: a main body and a latching body. The main body includes a first mounting portion having a stopper member and at least one first retaining unit, and a second mounting portion. The latching portion is movably disposed in the first mounting portion and includes at least one resilient portion and at least one second retaining unit. When one end of the latching body protrudes into the second mounting portion, the range of movement of the latching body spans from a position wherein the resilient portion abuts the stopper member to a position in wherein the second retaining unit abuts the first retaining unit. The main body is movably latched onto the DIN rail through the second mounting portion, and is fixed to a position on the DIN rail through one end of the latching body protruding into the second mounting portion.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: September 13, 2016
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chun-Lung Ho, Yi-Hsun Lee, Ming-Wei Ou, Yuan-Fu Lin
  • Patent number: 9379175
    Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: June 28, 2016
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
  • Patent number: 9349659
    Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Yasutoshi Okuno, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wei-Chun Tsai
  • Publication number: 20160141285
    Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.
    Type: Application
    Filed: October 16, 2015
    Publication date: May 19, 2016
    Inventors: Chien-Kai HUANG, Yuan-Fu CHUNG, Bo-Shih HUANG, Chang-Tzu WANG
  • Patent number: 9293331
    Abstract: In accordance with some embodiments, an assembly of an ion implanter system is provided. The assembly includes a control unit, a wafer holder and a detecting device. The wafer holder and the detecting device are respectively positioned at two sides of the control unit. The control unit is configured to drive the wafer holder and the detecting device to rotate about at least one rotation axis.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Fu Yang, Ping-Fang Chen
  • Publication number: 20160049462
    Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.
    Type: Application
    Filed: June 23, 2015
    Publication date: February 18, 2016
    Inventors: Chien-Kai Huang, Yuan-Fu Chung, Yuan-Hung Chung
  • Publication number: 20160047389
    Abstract: A fan shutter device includes a frame, multiple slats and multiple sleeves. The frame has a first side and a second side, each of which is formed with multiple assembling channels, multiple fixing holes and multiple displacement slots. Each slat has two extension sections and a connection shaft. Each of two ends of the connection shaft is formed with a connection socket. Each sleeve has a pivot pin and a sleeve section. The pivot pin is assembled and connected in the connection socket. Multiple fixing members are respectively passed through the fixing holes to directly fix the sleeves so that the first and second sides are prevented from deforming in assembling process. The slats are spaced from the frame by a gap without abrading with or interfering with the frame. The extension sections are disposed in the displacement slots, which restrict the rotational angle of the slats.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Inventors: Pei-Su Zhu, Mao-Lin Chen, Ming-Yuan Fu
  • Patent number: D755123
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: May 3, 2016
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chun-Lung Ho, Yi-Hsun Lee, Ming-Wei Ou, Yuan-Fu Lin, Wei-Min Tsao, Hung-Chih Wang