Abstract: A forming die includes a first die component with a male bead and a second die component with a female bead. The male bead and the female bead form a bead with a reverse bead geometry with the male bead having a groove and the female bead having a protrusion complimentary with the groove such that the protrusion is aligned with the groove when the male bead extends into the female bead. The male bead includes a push surface, a pair of sidewalls extending from the push surface to a main surface of the first die component, and the groove extends inwardly into the rib. And the female bead includes a stop surface and a pair of sidewalls extending from the stop surface to a main surface of the second die component, and the protrusion extends outwardly from the stop surface into the female bead.

Abstract: A forming die includes a first die component with a male bead and a second die component with a female bead. The male bead and the female bead form a bead with a reverse bead geometry with the male bead having a groove and the female bead having a protrusion complimentary with the groove such that the protrusion is aligned with the groove when the male bead extends into the female bead. The male bead includes a push surface, a pair of sidewalls extending from the push surface to a main surface of the first die component, and the groove extends inwardly into the rib. And the female bead includes a stop surface and a pair of sidewalls extending from the stop surface to a main surface of the second die component, and the protrusion extends outwardly from the stop surface into the female bead.

Abstract: A method of evaluating a sheet metal stamping simulation is provided. The method may include defining elements of a finite-element mesh representing a stamped panel, operating on the elements to simulate deformation of the panel during stamping to generate, for each of the elements, incremental differential major and minor plastic strain values, applying a weighting factor to temporally adjacent pairs of the values to generate smoothed values, deriving, from the smoothed values and for each of the elements, a plurality of plastic strain incremental ratios representing plastic flow direction of the elements during the deformation, and altering colors of a map based on the ratios to represent changes in severity of plastic deformation of the stamped panel.

Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.

Abstract: A method of evaluating a sheet metal stamping simulation is provided. The method may include defining elements of a finite-element mesh representing a stamped panel, operating on the elements to simulate deformation of the panel during stamping to generate, for each of the elements, incremental differential major and minor plastic strain values, applying a weighting factor to temporally adjacent pairs of the values to generate smoothed values, deriving, from the smoothed values and for each of the elements, a plurality of plastic strain incremental ratios representing plastic flow direction of the elements during the deformation, and altering colors of a map based on the ratios to represent changes in severity of plastic deformation of the stamped panel.

Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.

Abstract: Disclosed are an attenuated live vaccine against mycoplasmal pneumonia of swine (MPS) and use thereof. In the present invention, pathological lung tissues of swine having typical Mycoplasma hyopneumoniae (Mhp) infection and no obvious other pathogenic infections are screened, and subcultured 100 generations in lungs of newborn rabbits; then, Mhp strains are isolated and serially subcultured in a medium; and the Mhp strain AN306 is obtained by screening a plurality of strains, which is deposited with an accession number: CCTCC NO. M2012431. Also disclosed is a live vaccine formulation against MPS prepared on the basis of the attenuated strain and comprising live attenuated strain, a pharmaceutically acceptable carrier or excipient, and optionally an adjuvant and immunogens of other pathogens.

Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.

Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.

Abstract: Disclosed are an attenuated live vaccine against mycoplasmal pneumonia of swine (MPS) and use thereof. In the present invention, pathological lung tissues of swine having typical Mycoplasma hyopneumoniae (Mhp) infection and no obvious other pathogenic infections are screened, and subcultured 100 generations in lungs of newborn rabbits; then, Mhp strains are isolated and serially subcultured in a medium; and the Mhp strain AN306 is obtained by screening a plurality of strains, which is deposited with an accession number: CCTCC NO. M2014176. Also disclosed is a live vaccine formulation against MPS prepared on the basis of the attenuated strain and comprising live attenuated strain, a pharmaceutically acceptable carrier or excipient, and optionally an adjuvant and immunogens of other pathogens.

Abstract: A photo detector and related fabricating method are disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer. The patterned conductive layer is disposed on the dielectric layer. The inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region.

Abstract: A photo detector and related fabricating method are disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer. The patterned conductive layer is disposed on the dielectric layer. The inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region.

Abstract: An optical compensation film includes an optical film and a retardation film. The optical film provides a plate retardation in the direction of thickness (Rth), while the retardation film is disposed on the optical film. The retardation film includes first retarders and second retarders, wherein the first retarders are disposed on at least partial areas of the optical film and provide a first planar retardation (Ro1); the second retarders are disposed on partial areas of the optical film but outside the first retarders and provide a second planar retardation (Ro2) and the first planar retardation (Ro1) is different from the second planar retardation (Ro2). The above-mentioned optical compensation film is capable of compensating the displays for different display areas in a liquid crystal display panel. In addition, the present invention also provides a fabricating method of optical compensation film.

Abstract: A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

Abstract: A dual view display structure and a method for producing the same are provided. First, a display panel is provided. Then, a patterned barrier layer is formed on a transparent substrate. The transparent substrate with the patterned barrier layer is attached to the display panel. Because there is a gap between the display panel and the patterned barrier layer, a liquid transparent material is injected into the gap to form a transparent material layer to fill the gap. The invention can not only increase the viewing angles of the dual view display, but also increase the production yield.

Abstract: A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.

Abstract: A thin film transistor (TFT) structure is provided. The TFT comprises a gate, a first electrode, a second electrode, a dielectric layer, and a channel layer. By overlapping the area between the first electrode and the gate, the TFT structure acquires a parasitic capacitor that is unaffected by manufacture deviations. Therefore, the TFT needs no compensation capacitor, thereby, increasing the aperture ratio of the TFT.

Abstract: An optical reflective touch panel and pixels and a system thereof are provided. Each pixel of the optical reflective touch panel includes a display circuit and a sensing circuit. The display circuit controls the display of the pixel. The sensing circuit is coupled to the display circuit for sensing a sensitization state of the pixel during a turned-on period and a turned-off period of a backlight module and outputting a digital signal to notify an optical reflective touch panel system that whether the pixel is touched or not.

Abstract: In one aspect of the invention, the method of forming a TFT array panel includes forming a patterned first conductive layer on a substrate, forming a gate insulating layer on the patterned first conductive layer and the substrate, forming a patterned semiconductor layer on the gate insulating layer, forming a patterned second conductive layer, forming a patterned passivation layer on the patterned second conductive layer and the substrate, and forming a patterned transparent conductive layer on the patterned passivation layer.

Abstract: A thin film transistor (TFT) structure is provided. The TFT comprises a gate, a first electrode, a second electrode, a dielectric layer, and a channel layer. By overlapping the area between the first electrode and the gate, the TFT structure acquires a parasitic capacitor that is unaffected by manufacture deviations. Therefore, the TFT needs no compensation capacitor, thereby, increasing the aperture ratio of the TFT.