Abstract: An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number. The filter circuit further includes a logic gate configured to pass one of the pulses of the clock signal responsive to the output signal from the control circuit being enabled and filter another of the pulses responsive to the output signal from the control circuit being not enabled.

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include local latching circuits each having a retention circuit and a driving circuit. The retention circuit may be configured to provide local storage of broadcasted information for a down-stream circuit. The driving circuit may be configured to connect a first voltage and a second voltage to the retention circuit at different times across the broadcast and the local storage.

Abstract: Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ECC) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ECC control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. The fourth input/output nodes of the first ECC control circuit are coupled respectively to the first input/output nodes of the first memory cell array. The fifth input/output nodes of the first ECC are coupled respectively to the second input/output nodes of the second memory cell array.

Abstract: Apparatuses for executing interrupt refresh are described. An example apparatus includes: memory banks, a sampling timing generator circuit, bank sampling circuits and a command state signal generator circuit that provides a command state signal responsive to a command. Each memory bank includes a latch that stores an address for interrupt refresh. The sampling timing generator circuit receives an oscillation signal and provides a trigger signal of sampling the address. Each bank sampling circuit is associated with a corresponding memory bank. Each bank sampling circuit provides a sampling signal to the latch in the corresponding memory bank responsive to the trigger signal of sampling the address. The sampling timing generator circuit provides the trigger signal of sampling the address, responsive, at least in part, to the command state signal, and the latch stores the address, responsive, at least in part, to the at least one trigger signal of sampling the address.

Abstract: Methods, systems, and devices for low power mode for a memory device are described. A memory device may identify a pattern of data configured to be stored in an array of memory cells and determine if the pattern of data satisfies a criterion. The pattern of data may satisfy the criterion if each of the bits of data include a same logic value. If the pattern of data satisfies the criterion, the memory device may disable a driver of an internal bus of the memory device if the data satisfies the criterion, isolate a data line from the internal bus, or couple the data line with a voltage source, or a combination thereof. The memory device may further disable a signal of a clock tree based on identifying that the pattern of data satisfies the criterion.

Abstract: Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based on the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described.

Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.

Abstract: An edge memory array mat with access lines that are split, and a bank of sense amplifiers formed under the edge memory array may in a region that separates the access line segment halves. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes access line connectors configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: In an example semiconductor device, the voltage/temperature conditions of the semiconductor device and associated calibration codes of multiple instances of ZQ calibrations are pre-stored in a register array. When a pre-stored voltage/temperature condition occurs again, ZQ calibration is not performed. Instead, the associated pre-stored calibration code is retrieved from the register array and provided to the IO circuit. When a voltage/temperature condition of the semiconductor device does not match any pre-stored voltage/temperature condition in the register array, a ZQ calibration is performed. When the ZQ calibration is performed, a register in the register array is selected according to an update policy and updated by the calibration code newly provided by the ZQ calibration along with the voltage/temperature condition at the time when the ZQ calibration is performed.

Abstract: A system information obtaining method, a UE and a network side device are provided. The method includes: receive first scheduling information of on-demand SI sent by a network side device; obtain the on-demand SI sent by the network side device based on the first scheduling information.

Abstract: A transmission method of system information, a user equipment, a network side device, a system and a storage medium are provided. The method includes: receiving, by the UE, system information sent by a network side device, the system information is part of system information of the network side device; sending, by the UE, a request message to the network side device, wherein the request message is used to request the system information required by the UE; receiving by the UE, the system information required by the UE in on-demand system information sent by the network side device, wherein the on-demand system information is another part of system information of the network side device other than the part of system information of the network side device.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank may receive access commands and then periodically enter a refresh mode, where auto-refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped.

Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.

Abstract: A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.

Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.

Abstract: Fuse latch circuits and related systems, methods, and apparatuses are disclosed. An apparatus includes a half interlock latch circuit including a first half and a second half. The first half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the second half of the half interlock latch circuit in a driven state. The second half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the first half of the half interlock latch circuit in a driven state.

Abstract: An apparatus having memory dies with a memory cell array divided into a plurality of data segments. A stagger circuit selects a common command signal and sets a column access signal to select a data segment to be accessed based on the common command signal and/or an individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment. A data bus connects the memory cell arrays to form data units with each data unit including a data segment from each memory cell array and configured such that the data segments are connected in parallel to the data bus and use a same line of the data bus. The stagger circuits are configured such that data segments identified for activation in the plurality of memory dies are not part of a same data unit.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for fuse latch and match circuits. A memory may include a number of fuse registers, each of which is associated with a line of redundant memory cells. An address may be stored in fuse latches of the fuse register. A dynamic logic circuit may activate one of the fuse registers and a match logic circuit may compare the address stored in the activated fuse register to an address received as part of an access operation to determine if the redundant memory cells should be accessed. The fuse latches may be floated during a power up operation. The dynamic logic circuit may control a timing of the activation and comparison operation.