Patents by Inventor Yuan He

Yuan He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • APPARATUSES AND METHODS FOR DYNAMIC TARGETED REFRESH STEALS
    Publication number: 20220189539
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank ma receive access commands and then periodically enter a refresh mode, where auto refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped.
    Type: Application
    Filed: March 8, 2022
    Publication date: June 16, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Liang Li, Yu Zhang, Yuan He
  • Column selector architecture with edge mat optimization
    Patent number: 11361814
    Abstract: A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Hiroshi Akamatsu
  • ARTICLE IDENTIFICATION METHOD AND DEVICE, AND COMPUTER READABLE STORAGE MEDIUM
    Publication number: 20220180621
    Abstract: An article identification method and device, and a computer readable storage medium. The article identification method comprises: receiving an article type selection instruction triggered by a user, and acquiring a target image acquisition frame corresponding to a target type selected by the user (10); acquiring an imaged image of an article to be identified in the target image acquisition frame (20); performing feature comparison on the imaged image and pre-stored feature information in a preset database, and determining, according to the comparison result, target pre-stored feature information matching the imaged image (30); and determining an identification code of said article (40) according to the target pre-stored feature information. The solution can simplify the implementation process of article identification, and reduce the difficulty of article identification.
    Type: Application
    Filed: June 5, 2020
    Publication date: June 9, 2022
    Inventors: Yongfeng XI, Yuan HE, Yijie HAO, Guozhong CAO, Chenglong LI
  • APPARATUS WITH LATCH CORRECTION MECHANISM AND METHODS FOR OPERATING THE SAME
    Publication number: 20220164251
    Abstract: Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a fuse array configured to provide non-volatile storage of fuse data and (2) local latches configured to store the fuse data during runtime of the apparatus. The apparatus may further include an error processing circuit configured to determine error detection-correction data for the fuse data. The apparatus may subsequently broadcast data stored in the local latches to the error processing circuit to determine, using the error detection-correction data, whether the locally latched data has been corrupted. The error processing circuit may generate corrected data to replace the locally latched data based on determining corruption in the locally latched data.
    Type: Application
    Filed: November 20, 2020
    Publication date: May 26, 2022
    Inventors: Yuan He, Jiyun Li
  • Portable manual vertical milling key duplicating machine
    Patent number: 11338375
    Abstract: A portable manual vertical milling key duplicating machine comprising a body, a main axis component, a guide component, a clamping component, a feeding component, a power storage unit, a display unit and an electric control unit. This solution provides a pre-positioned precise guide mechanism and an adjustable handrail and is capable of improving the precision of key processing in multiple aspects and increasing stability during key processing. It has a compact structure with an upper/lower separate two-way sliding table configuration, thereby substantially reducing the machine size, and the body is divided into three areas, thereby ensuring good protection.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: May 24, 2022
    Assignee: Shenzhen Xhorse Electronics Co., Ltd.
    Inventors: Yongfeng Xi, Yuan He, Yijie Hao, Chenglong Li, Guozhong Cao
  • SUB-THRESHOLD CURRENT REDUCTION CIRCUIT SWITCHES AND RELATED APPARATUSES AND METHODS
    Publication number: 20220158631
    Abstract: Sub-threshold current reduction circuit (SCRC) switches and related apparatuses and methods are disclosed. An apparatus includes a first set of SCRC switches and a second set of SCRC switches electrically connected between power supply lines and power reception lines. The first set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and the second operational mode. The second set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and electrically isolate the power supply lines from the power reception lines in the second operational mode. Activation of the first set of SCRC switches is staggered in time with activation of the second set of SCRC switches. The second set of SCRC switches is spaced among the first set of SCRC switches.
    Type: Application
    Filed: November 16, 2020
    Publication date: May 19, 2022
    Inventors: Yoshihiro Shibata, Sachiko Edo, Takuya Nakanishi, Yuan He, Hiroshi Akamatsu
  • APPARATUSES INCLUDING MEMORY REGIONS HAVING DIFFERENT ACCESS SPEEDS AND METHODS FOR USING THE SAME
    Publication number: 20220157372
    Abstract: Apparatuses, systems, and methods for faster memory access regions. A memory array may have a fiat bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 19, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Yuan He, Daigo Toyama, Chikara Kondo, Takehiro Hasegawa
  • COLUMN SELECTOR ARCHITECTURE WITH EDGE MAT OPTIMIZATION
    Publication number: 20220139444
    Abstract: A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Inventors: Yuan He, Hiroshi Akamatsu
  • Apparatuses and methods for dynamic targeted refresh steals
    Patent number: 11302377
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank may receive access commands and then periodically enter a refresh mode, where auto-refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Liang Li, Yu Zhang, Yuan He
  • Method for acquiring system information, user equipment and network side device
    Patent number: 11304120
    Abstract: A method for acquiring a system information SI, a user equipment UE and a network side device. The method includes: receiving, by the UE, an SI table index from the network side device; and acquiring, by the UE, the SI based on the SI table index and a pre-acquired SI table. The SI table includes SI table indices, SI and a parameter configuration of the SI.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: April 12, 2022
    Assignee: DATANG MOBILE COMMUNICATIONS EQUIPMENT CO., LTD.
    Inventor: Yuan He
  • THREE-DIMENSIONAL FUSE ARCHITECTURES AND RELATED SYSTEMS, METHODS, AND APPARATUSES
    Publication number: 20220108995
    Abstract: Apparatuses, methods, and computing systems relating to three-dimensional fuse architectures are disclosed. An apparatus includes a semiconductor substrate, a fuse array on or in the semiconductor substrate, and fuse circuitry on or in the semiconductor substrate. The fuse array includes fuse cells. The fuse circuitry is configured to access the fuse cells. The fuse circuitry is offset from the fuse array such that the fuse circuitry is disposed between the semiconductor substrate and the fuse array, or the fuse array is disposed between the semiconductor substrate and the fuse circuitry.
    Type: Application
    Filed: October 5, 2020
    Publication date: April 7, 2022
    Inventors: Yuan He, Daigo Toyama
  • SECURITY INSPECTION DEVICE
    Publication number: 20220099858
    Abstract: An inspection device is provided, includes a first vehicle body, a radiation source, arranged in the first vehicle body, a second vehicle body, a protective wall, arranged on the second vehicle body, a boom, and detectors, arranged on the boom, and the boom is rotatably connected to the first vehicle body and the second vehicle body, forms an inspection passage together with the first vehicle body and the second vehicle body. The inspection device can improve the adaptability.
    Type: Application
    Filed: January 6, 2020
    Publication date: March 31, 2022
    Inventors: Chunguang ZONG, Quanwei SONG, Kejin GAO, Shangmin SUN, Junping SHI, Yuan HE, Yu HU, Feng WANG, Jinguo CAO
  • Charge transfer between gate terminals of subthreshold current reduction circuit transistors and related apparatuses and methods
    Patent number: 11290103
    Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods is disclosed. An apparatus includes a pull-up SCRC transistor, a pull-down SCRC transistor, and a charge transfer circuit. The pull-up SCRC transistor includes a pull-up gate terminal. The pull-down SCRC transistor includes a pull-down gate terminal. The charge transfer circuit is electrically connected between the pull-up gate terminal and the pull-down gate terminal. The charge transfer circuit is configured to transfer charge between the pull-up gate terminal and the pull-down gate terminal.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Yuan He, Toru Ishikawa
  • DISPLAY MOTHERBOARD, FABRICATING METHOD AND ALIGNING METHOD OF DISPLAY MOTHERBOARD
    Publication number: 20220093692
    Abstract: The present disclosure provides a display motherboard, a method for fabricating the same, and a method for aligning the same. The display motherboard includes an array substrate on which an alignment mark and a color film layer are provided. A portion of a black matrix of the color film layer in an alignment mark area includes a first light-shielding portion and a second light-shielding portion. The first light-shielding portion covers the alignment mark, and the second light-shielding portion covers an area outside the alignment mark, where upper surfaces of the first light-shielding portion and the second light-shielding portion are not in the same plane. When the display motherboard is aligned in the subsequent processes, since the black matrix forms the same pattern as the alignment mark due to a height step, when the exposure machine exposures, the pattern can be directly captured for alignment.
    Type: Application
    Filed: April 13, 2021
    Publication date: March 24, 2022
    Inventors: Shuo LI, Ling SHI, Yuan HE
  • Apparatus with latch balancing mechanism and methods for operating the same
    Patent number: 11282569
    Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include local latching circuits each having a retention circuit and a driving circuit. The retention circuit may be configured to provide local storage of broadcasted information for a down-stream circuit. The driving circuit may be configured to connect a first voltage and a second voltage to the retention circuit at different times across the broadcast and the local storage.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Hiroshi Akamatsu
  • Integrated Assemblies
    Publication number: 20220084578
    Abstract: Some embodiments include an integrated assembly having a memory deck over a base, and having an array of memory cells along the memory deck. The array includes rows which extend along a row direction and columns which extend along a column direction. Wordlines are along the rows and digit-lines are along the columns. CONTROL circuitry is along the base and includes WORDLINE DRIVER circuitry coupled with the wordlines. The CONTROL circuitry is subdivided amongst banks. The banks are elongated along the row direction. Each of the banks is subdivided amongst a series of sections, with the sections being arranged in section rows which extend along the row direction. Each of the sections includes a series of patches, with the patches including INPUT/OUTPUT circuitry. The patches are arranged in groups, with the groups sharing portions of the WORDLINE DRIVER circuitry.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Jiyun Li, Yuan He
  • SECURITY INSPECTION DEVICE AND TRANSFER METHOD THEREFOR
    Publication number: 20220082723
    Abstract: The present disclosure relates to a security inspection device and a transfer method, and the security inspection device includes an arm frame, provided with detectors, and configured to form an inspection channel, a first compartment, internally provided with a radiation source and connected with the arm frame, a protection wall, connected with the first compartment or the arm frame, and configured to perform radiation protection for an object to be protected, and a tire, configured to enable the security inspection device to move relative to the ground, and the arm frame, the first compartment and the protection wall are set to be transported together in a connected state.
    Type: Application
    Filed: January 3, 2020
    Publication date: March 17, 2022
    Inventors: Quanwei SONG, Xuping FAN, Junping SHI, Yuan HE, Hui MENG, Chunguang ZONG, Yu HU, Shangmin SUN, Jinguo CAO
  • APPARATUSES AND METHODS TO PERFORM LOW LATENCY ACCESS OF A MEMORY
    Publication number: 20220068329
    Abstract: An exemplary memory is configurable to operate in a low latency mode through use of a low latency register circuit to execute a read or write command, rather performing a memory army access to execute the read or write command. A control circuit determines whether an access command should be performed using the low latency mode of operation (e.g., first mode of operation) or a normal mode of operation (e.g., second mode of operation). In some examples, a processor unit directs the memory to execute an access command using the low latency mode of operation via one or more bits (e.g., a low latency enable bit) included in the command and address information.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 3, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Yuan He, Daigo Toyama
  • BUBBLE BREAK REGISTER IN SEMICONDUCTOR DEVICE
    Publication number: 20220066681
    Abstract: An exemplary register circuit includes a plurality of slots to store respective addresses and data pairs. During a write operation, each slot of a plurality of slots preceding a particular slot of the plurality of slots indicated as empty is shifted by one slot to fill the particular slot such that a first end slot of the plurality of slots is made available to receive a new write address and data pair. Each slot of the plurality of slots subsequent to the particular slot retains existing address and data pairs.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 3, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Yuan He, Pu Yang
  • COMPOSITIONS AND METHODS FOR HIGHLY EFFICIENT GENETIC SCREENING USING BARCODED GUIDE RNA CONSTRUCTS
    Publication number: 20220064633
    Abstract: Compositions, kits and methods are provided for genetic screening using one or more sets of guide RNA constructs having internal barcodes (“iBAR”). Each set has three or more guide RNA constructs targeting the same genomic locus, but embedded with different iBAR sequences.
    Type: Application
    Filed: December 20, 2019
    Publication date: March 3, 2022
    Applicants: Peking University, Edigene Biotechnology Inc.
    Inventors: Wensheng WEI, Shiyou ZHU, Zhongzheng CAO, Zhiheng LIU, Yuan HE, Pengfei YUAN