Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell, and a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip. The access control circuit is configured to activate a first enable signal during the refresh operation. The second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.

Abstract: Bit line equalization driver circuits and related apparatuses, methods, and computing systems are disclosed. An apparatus includes an output inverter including a pull-up transistor and a pull-down transistor electrically connected in series between a pull-up node and a pull-down node. An output node is electrically connected between the pull-up transistor and the pull-down transistor. The pull-down transistor includes a short length transistor having a degradation voltage potential across the pull-down transistor below which the pull-down transistor is configured to operate to avoid degradation of the pull-down transistor. The apparatus also includes biasing circuitry configured to control voltage potentials at the pull-up node and the pull-down node to enable the output inverter to assert, at the output node, an output voltage potential that is greater than the degradation voltage potential higher than a low power supply voltage potential at the low power supply node.

Abstract: An apparatus having memory dies with a memory cell array divided into a plurality of data segments. A stagger circuit selects a common command signal and sets a column access signal to select a data segment to be accessed based on the common command signal and/or an individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment. A data bus connects the memory cell arrays to form data units with each data unit including a data segment from each memory cell array and configured such that the data segments are connected in parallel to the data bus and use a same line of the data bus. The stagger circuits are configured such that data segments identified for activation in the plurality of memory dies are not part of a same data unit.

Abstract: In an example semiconductor device, the voltage/temperature conditions of the semiconductor device and associated calibration codes of multiple instances of ZQ calibrations are pre-stored in a register array. When a pre-stored voltage/temperature condition occurs again, ZQ calibration is not performed. Instead, the associated pre-stored calibration code is retrieved from the register array and provided to the IO circuit. When a voltage/temperature condition of the semiconductor device does not match any pre-stored voltage/temperature condition in the register array, a ZQ calibration is performed. When the ZQ calibration is performed, a register in the register array is selected according to an update policy and updated by the calibration code newly provided by the ZQ calibration along with the voltage/temperature condition at the time when the ZQ calibration is performed.

Abstract: Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.

Abstract: The disclosure relates to a traction device and a traction method. The traction device includes: a support chassis; a swing arm, one end of the swing arm is rotatably connected to the support chassis by a rotating shaft such that the swing arm can be switched in a retracted state and a deployed state, wherein the swing arm in the deployed state is adapted to drive the wheel of the vehicle to rotate and tow the vehicle; a driving mechanism, connected to the swing arm, wherein the driving mechanism is capable of driving the swing arm to horizontally rotate around the rotating shaft to switch the swing arm between the retracted state and the deployed state; and a rolling assembly, disposed on a side of the support chassis and being capable of preventing the wheel from contacting with the side of the support chassis when the vehicle is towed.

Abstract: The present disclosure relates to a method, a device, and a storage medium for vehicle intelligent driving control. The vehicle intelligent driving control method comprises: collecting, by means of a vehicle-mounted camera of a vehicle, a video stream of a road image of a scene where the vehicle is; detecting a target object in the road image to obtain a bounding box of the target object; determining, in the road image, a free space for the vehicle; adjusting the bounding box of the target object according to the free space; and carrying out intelligent driving control on the vehicle according to the adjusted bounding box. The bounding box of the target object can be used to identify the position and determine the actual position of the target object more precisely, such that intelligent driving control can be carried out on the vehicle more accurately.

Abstract: In some examples, a system may include a plurality of memory blocks, a first data bus coupled to the plurality of memory blocks in a memory device, a second data bus coupled to the plurality of memory blocks, a controller configured to perform memory read and write operations on the plurality of memory blocks via the first data bus, and a non-volatile storage (NVS) data transfer circuit configured to transfer data in a first memory block of the plurality of memory blocks to a NVS device via the second data bus. The first memory block may be a cold data block least accessed among the plurality of memory blocks. The cold data transfer may be performed via the second data bus when a different memory block is being accessed via the first data bus concurrently. The second data bus may be a fuse bus in the memory device.

Abstract: An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: Embodiments of the present invention discloses a network positioning method and related equipments, the method includes: determining, by a first device, an auxiliary UE from a candidate set, the candidate set is within the end-to-end range of the first device, determining, by the first device, whether the end-to-end range of the first device is less than a range configured by a network device; based on the determination that the end-to-end range of the first device is less than a range configured by a network device, setting, by the first device, position information of the first device as the position information of the auxiliary UE. The technical solution provided by the present invention can effectively enhance the network positioning precision.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier with a sensing circuit configured to precharge a connected extended digit line. A balancing circuit may be connected to the extended digit line opposite the sensing circuit. The balancing circuit may be configured to selectively connect the extended digit line to a precharging source to precharge the extended digit line.

Abstract: An edge memory array mat with access lines that are split, and a bank of sense amplifiers formed under the edge memory array may in a region that separates the access line segment halves. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes access line connectors configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

Abstract: Apparatus and methods of reducing dock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control circuit. The clock control circuit includes a command/address domain configured to selectively provide a command/address clock signal based, at least in part, on a chip select signal. The clock control circuit further includes a command domain circuit configured to selectively provide a command clock signal based, at least in part, on the chip select signal. The clock control circuit further includes a column latency domain circuit configured to selectively provide a column latency clock signal based, at least in part, on a memory command. The clock control circuit further includes a four phase domain circuit configured to selectively provide a four phase clock signal based, at least in part, on the memory command.

Abstract: Methods and systems for descriptor guided fast marching method based image analysis and associated systems are disclosed. A representative image processing method includes processing an image of a microelectronic device using a fast marching algorithm to obtain arrival time information for the image. The arrival time information is analyzed using a targeted feature descriptor to identify targeted features. The detection of defects is facilitated by segmenting the image. The segmented image can be analyzed to identify targeted features which are then labeled for inspection.

Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.

Abstract: A method for acquiring a system information SI, a user equipment UE and a network side device. The method includes: receiving, by the UE, an SI table index from the network side device; and acquiring, by the UE, the SI based on the SI table index and a pre-acquired SI table. The SI table includes SI table indices, SI and a parameter configuration of the SI.

Abstract: A fork-arm lift tractor includes a vehicle body, a supporting plate disposed above the vehicle body, a lifting device for driving the supporting plate to be lifted, a front and rear fork-arm assemblies, a front and rear fork-arm drive assemblies. The front fork-arm assembly includes two front fork-arms rotatably disposed at the supporting plate. The rear fork-arm assembly includes two rear fork-arms rotatably disposed at the supporting plate, and the front and rear fork-arms may be deployed or retracted from both sides of the supporting plate. The front fork-arm driving assembly includes a front transmission part, and a front power device disposed at the supporting plate and may drive the front transmission part to move horizontally linearly so as to rotate the two front fork-arms. The rear fork-arm driving assembly has almost the same structure of the front fork-arm driving assembly and is used to rotate the two rear fork-arms.

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier with a sensing circuit configured to precharge a connected extended digit line. A balancing circuit may be connected to the extended digit line opposite the sensing circuit. The balancing circuit may be configured to selectively connect the extended digit line to a precharging source to precharge the extended digit line.