Abstract: An electronic device is provided. The electronic device includes a substrate, a plurality of diodes, at least one transistor, a chip, a conductive layer and a conductive layer. The substrate has a first surface and a second surface opposite to the first surface. The plurality of diodes are disposed on the first surface of the substrate. The at least one transistor is disposed on the first surface of the substrate and electrically connected to at least one of the plurality of diodes. The chip is disposed on the second surface of the substrate and electrically connected to the at least one transistor. The conductive layer is disposed between the substrate and the chip. The protection layer is disposed between the conductive layer and the chip. Moreover, the protection layer has an opening and through which the chip is electrically connected to the conductive layer.

Abstract: A multi-chip package includes a ball-grid-array (BGA) substrate; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the ball-grid-army (BGA) substrate; a plurality of first metal bumps between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of first metal bumps has a top end joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end joining the ball-grid-array (BGA) substrate; a non-volatile-memory (NVM) integrated-circuit (IC) chip package over the ball-grid-array (BGA) substrate, wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip package comprises a circuit substrate, a non-volatile-memory (NVM) integrated-circuit (IC) chip over and coupling to the circuit substrate and a plurality of second metal bumps under and on the circuit substrate and bonded to the ball-grid-array (BGA) substrate; and a plurality of tin-containing bumps under and on the bal

Abstract: A multi-chip package includes a first semiconductor integrated-circuit (IC) chip comprising a first input/output (I/O) circuit therein; and an input/output (I/O) integrated-circuit (IC) chip comprising a second input/output (I/O) circuit therein coupling to the first input/output (I/O) circuit, a third input/output (I/O) circuit therein, a voltage-level shift-up circuit therein configured to shift data from a first voltage level at a first node thereof coupling to the second input/output (I/O) circuit to a second voltage at a second node thereof coupling to the third input/output (I/O) circuit and a voltage-level shift-down circuit therein configured to shift data from the second voltage level at the second node coupling to the third input/output (I/O) circuit to the first voltage level at the first node coupling to the second input/output (I/O) circuit, wherein the second voltage level is higher than the first voltage level.

Abstract: A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top sur

Abstract: A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the s

Abstract: A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC c

Abstract: A method includes forming a first capacitor electrode; forming a first oxygen-blocking layer on the first capacitor electrode; forming an capacitor insulator layer on the first oxygen-blocking layer; forming a second oxygen-blocking layer on the capacitor insulator layer; forming a second capacitor electrode on the second oxygen-blocking layer; and forming a first contact plug that is electrically coupled to the first capacitor electrode and a second contact plug that is electrically coupled to the second capacitor electrode.

Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, the fin comprising alternately stacking first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form spaces each between the second semiconductor layers, forming a gate dielectric layer wrapping around each of the second semiconductor layers, forming a fluorine-containing layer on the gate dielectric layer, performing an anneal process to drive fluorine atoms from the fluorine-containing layer into the gate dielectric layer, removing the fluorine-containing layer, and forming a metal gate on the gate dielectric layer.

Abstract: A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the s

Abstract: A trim circuit for an e-fuse unit includes: a mirroring circuit for receiving an enable signal, when triggered by the enable signal, the mirroring circuit generating a driving voltage; and a driving transistor coupled to the mirroring circuit, in response to the driving voltage from the mirroring circuit, the driving transistor turning ON to generate a MOS current to an output node, wherein the output node is coupled to the e-fuse unit, and in response to the MOS current from the output node, the e-fuse unit is burned out.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Abstract: A trim circuit for an e-f use unit includes: a mirroring circuit for receiving an enable signal, when triggered by the enable signal, the mirroring circuit generating a driving voltage; and a driving transistor coupled to the mirroring circuit, in response to the driving voltage from the mirroring circuit, the driving transistor turning ON to generate a MOS current to an output node, wherein the output node is coupled to the e-fuse unit, and in response to the MOS current from the output node, the e-fuse unit is burned out.

Abstract: An over-current protection device comprises first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, a conductive filler and a titanium-containing inner filler. The polymer matrix has a fluorine-free polyolefin-based polymer. The titanium-containing inner filler has a compound represented by a general formula of MTiO3, wherein the M represents transition metal or alkaline earth metal. The total volume of the PTC material layer is calculated as 100%, and the titanium-containing inner filler accounts for 1-9% by volume of the PTC material layer.

Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, a conductive filler, and a titanium-containing dielectric filler. The polymer matrix has a fluoropolymer. The titanium-containing dielectric filler has a compound represented by a general formula of MTiO3, wherein the M represents transition metal or alkaline earth metal. The total volume of the PTC material layer is calculated as 100%, and the titanium-containing dielectric filler accounts to for 5-15% by volume of the PTC material layer.

Abstract: A device includes a substrate having a first surface and a second surface opposite to the first surface; a thin-film transistor array disposed on the first surface, including a plurality of transistors; a plurality of diodes disposed on the thin-film transistor array; a plurality of conductive structures penetrating through the substrate from the first surface to the second surface, wherein the plurality of conductive structures are corresponding to the plurality of diodes and electrically connected to the plurality of diodes; a driver unit disposed on the second surface of the substrate; a patterned conductive layer disposed between the substrate and the driver unit; a protection layer disposed on the patterned conductive layer, wherein the protection layer has an opening that exposes the patterned conductive layer; and a conductive material disposed in the opening.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: The present disclosure provides an electronic apparatus including a first surface, a second surface, a third surface, a plurality of conductive elements, and an encapsulant. The second surface is nonparallel to the first surface. The third surface is distinct from the first surface and the second surface. The plurality of conductive elements are exposed from the second surface. The encapsulant covers the third surface and exposes the first surface and the second surface.

Abstract: A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling