Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer correspondingly formed below the first spiral trace layer, wherein the inter-metal dielectric layer has a separating region to divide the second spiral trace layer into a plurality of line segments, and wherein each of a plurality of first slit openings and each of a plurality of second slit openings pass through a corresponding line segment, and extend in an extending direction of a length of the corresponding line segment.

Abstract: A ceiling fan and a surrounding device thereof are provided. The ceiling fan includes a main body, a bracket set connected to the main body, and a surrounding device connected to the bracket set. The main body includes a main shaft, a motor, and a plurality of ceiling fan blades. The bracket set includes a plurality of brackets, and each of the brackets has one end connected to the main shaft. The surrounding device is connected to another end of each of the brackets that is relatively far away from the main shaft, and the surrounding device is roundly arranged around and spaced apart from an end of each of the ceiling fan blades that is relatively far away from the motor. The surrounding device includes at least one functional component that is configured to disinfect or sterilize air or to provide lighting.

Abstract: The present disclosure relates to a compound of Formula I, or a geometric isomer, enantiomer, diastereomer, racemate, atropisomer, pharmaceutically acceptable salt, prodrug or solvate thereof. The present disclosure further relates to a composition comprising the compound of Formula (I). The compound and the composition described herein can be used to inhibit NADPH oxidase activity.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other.

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.

Abstract: A method includes forming a first trench and a second trench in a base structure. The first trench has a first aspect ratio, and the second trench has a second aspect ratio lower than the first aspect ratio. A deposition process is then performed to deposit a layer. The layer includes a first portion extending into the first trench, and a second portion extending into the second trench. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness by a first difference. The method further includes performing an etch-back process to etch the layer. After the etch-back process, the first portion has a third thickness, and the second portion has a fourth thickness. A second difference between the third thickness and the fourth thickness is smaller than the first difference.

Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Abstract: Embodiments include a nanoFET device and method for forming the same, the nanoFET having channel regions which have been thinned during a gate replacement process to remove etching residue. In some embodiments, the channel regions become dog bone shaped. In some embodiments, the ends of the channel regions have vertical protrusions or horns resulting from a previous trimming process which is performed prior to depositing sidewall spacers.

Abstract: A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the

Abstract: A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Abstract: A method for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

Abstract: A ceiling fan and a surrounding device thereof are provided. The ceiling fan includes a main body, a bracket set connected to the main body, and a surrounding device connected to the bracket set. The main body includes a main shaft, a motor, and a plurality of ceiling fan blades. The bracket set includes a plurality of brackets, and each of the brackets has one end connected to the main shaft. The surrounding device is connected to another end of each of the brackets that is relatively far away from the main shaft, and the surrounding device is roundly arranged around and spaced apart from an end of each of the ceiling fan blades that is relatively far away from the motor. The surrounding device includes at least one functional component that is configured to disinfect or sterilize air or to provide lighting.

Abstract: A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling

Abstract: A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space

Abstract: Disclosed herein is a method of using a hyaluronan conjugate, which includes a hyaluronic acid (HA), a sex hormone, and a linker for coupling one of the disaccharide units of the HA and the sex hormone. The hyaluronan conjugates are used in treating neurodegenerative diseases.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first spiral trace layer. The inter-metal dielectric layer has a separating region to divide the second spiral trace layer into line segments. First slit openings each passes through a corresponding line segment, and extends in an extending direction of a length of the corresponding line segment.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Abstract: A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer