Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The method includes depositing a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench using an atomic layer deposition process. The method includes forming a gate electrode layer over the gate dielectric layer. The method includes removing the gate dielectric layer and the gate electrode layer outside of the wide trench and the narrow trench.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric (IMD) layer, and first and second winding portions symmetrically arranged in the IMD layer and the insulating redistribution layer with respect to a symmetrical axis. The first and second winding portions each includes at least first and second semi-circular stacking layers arranged from the inside to the outside and in concentricity. The first and second semi-circular stacking layers each has a first trace layer in the insulating redistribution layer and a second trace layer in the IMD layer and correspondingly formed below the first trace layer. A first slit opening passes through the second trace layer and extends in the extending direction of the length of the second trace layer.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first spiral trace layer. The inter-metal dielectric layer has a separating region to divide the second spiral trace layer into line segments. First slit openings each passes through a corresponding line segment, and extends in an extending direction of a length of the corresponding line segment.

Abstract: A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.

Abstract: A ball joint holder with limiting element includes a lower base, an upper base covered to the lower base, a ball shaft and a limiting element. The ball shaft has a rotation rod, and a ball body located around a lower end of the rotation rod. A lower end of the rotation rod protrudes outward to form a limiting block. Two opposite ends of the limiting element are pivotally connected with the lower base and the upper base. The limiting element opens a limiting groove. One of inner surfaces of a front wall and a rear wall of the limiting groove is defined as a limiting surface. The lower end of the rotation rod and the limiting block are received in the limiting groove. The limiting block is capable of abutting against the limiting surface.

Abstract: A micro heat transfer component includes a bottom metal plate; a top metal plate; a plurality of sidewalls each having a top end joining the top metal plate and a bottom end joining the bottom metal plate, wherein the top and bottom metal plates and the sidewalls form a chamber in the micro heat transfer component; a plurality of metal posts in the chamber and between the top and bottom metal plates, wherein each of the metal posts has a top end joining the top metal plate and a bottom end joining the bottom metal plate; a metal layer in the chamber, between the top and bottom metal plates and intersecting each of the metal posts, wherein a plurality of openings are in the metal layer, wherein a first space in the chamber is between the metal layer and bottom metal plate and a second space in the chamber is between the metal layer and top metal plate; and a liquid in the first space in the chamber.

Abstract: A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC c

Abstract: A head band; and a pair of earmuffs being respectively mounted on two ends of the head band, each of the earmuffs has a speaker and a cushion. The cushion has an annular elastic portion protruded from a peripheral of the cushion and a chamber is surrounded by the annular elastic portion. The speaker has a back housing. A circuit board mounted to the back housing. A connector mounted on the circuit board. A speaker unit mounted to the back housing. A front housing covers the speaker unit and is assembled with the back housing. An opening penetrated through the front housing. A pressure sensor is disposing in the opening. A flexible circuit board connected between the pressure sensor and the connector of the circuit board. The cushion attached to the front housing. The pressure sensor is located in the chamber.

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.

Abstract: A display device is provided. The display device includes a substrate having a first surface and a second surface opposite to the first surface, a plurality of light-emitting units disposed on the first surface of the substrate, and a plurality of conductive structures extending into the substrate from the second surface of the substrate. The plurality of conductive structures are electrically connected to the plurality of light-emitting units.

Abstract: A method and system is for searching a database to identify structures of molecular compounds from mass spectrometry data. Operations of the method and system include receiving a query for a target molecular structure in the database, the query representing a query spectrum; accessing a machine learning model trained with molecule-spectrum pairs; inputting the query spectrum into the machine learning model; generating, from the machine learning model, a score for each of one or more molecular structures, each score representing a probability that a molecular structure corresponds to the query spectrum; selecting, based on each of the scores, a small molecule; and outputting, on a user interface, a representation of the small molecule.

Abstract: An electronic device includes a substrate, a first conductive pad and a chip. The first conductive pad is disposed on the substrate. The chip includes a second conductive pad electrically connected to the first conductive pad, and the first conductive pad is disposed between the substrate and the second conductive pad. The first conductive pad has a first groove.

Abstract: An on-chip inductor structure includes first and second winding portions symmetrically arranged in an insulating layer by a symmetrical axis. Each of the first and second winding portions includes first and second semi-circular conductive lines concentrically arranged from the inside to the outside. First and second input/output conductive portions are disposed in the insulating layer along the extending direction of the symmetrical axis, to respectively and electrically couple the first ends of the outermost semi-circular conductive lines. A conductive branch structure is disposed in the insulating layer along the symmetrical axis and between the first and second input/output conductive portions, and electrically coupled to first ends of the innermost semi-circular conductive lines. The conductive branch structure has a grounded first end and a second end is electrically coupled to a circuit and is opposite the first end of the conductive branch structure.

Abstract: A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.