Patents by Inventor Yuan Liang

Yuan Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080156520
    Abstract: A complex printed circuit board structure including a flexible printed wiring board and a heat-dissipating substrate bonded with the flexible printed wiring board. Parts of surface material of the flexible printed wiring board is removed to form depressions or through holes for laying electronic elements therein. The surfaces of the electronic elements can at least partially get closer to or directly contact the heat-dissipating substrate through the depressions or through holes of the flexible printed wiring board. Therefore, the heat generated by the electronic elements can be more quickly and directly conducted to the heat-dissipating substrate and dissipated at high efficiency.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 3, 2008
    Applicant: Bothhand Enterprise Inc.
    Inventors: Chang-Liang Lin, Chi-Lung Lee, Hui-Yuan Liang, Jiu-Yan Yan
  • Publication number: 20080123376
    Abstract: A DC/AC adapter assembly has a DC/AC adapter and a cable. The cable transmits a power-overloading signal to the DC/AC adapter indicating whether power-overloading is occurring in the cable. The DC/AC adapter includes a controller circuit for controlling and adjusting an output alternating current of the DC/AC adapter based on the power-overloading signal to reduce power-overloading occurring in the cable.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 29, 2008
    Inventors: Lien-Hsun Ho, Yuan-Liang Hsu, Shou-Ting Yeh, Chuan-Hsing Wu, Grant Chen
  • Publication number: 20080088009
    Abstract: A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.
    Type: Application
    Filed: December 10, 2007
    Publication date: April 17, 2008
    Inventors: Jiangqi He, Yuan-Liang Li, Michael Walk
  • Patent number: 7358607
    Abstract: Arrangements are used for minimizing signal path discontinuities.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: April 15, 2008
    Assignee: Intel Corporation
    Inventors: David G. Figueroa, Yuan-Liang Li
  • Publication number: 20080079136
    Abstract: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.
    Type: Application
    Filed: November 20, 2007
    Publication date: April 3, 2008
    Applicant: INTEL CORPORATION
    Inventor: Yuan-Liang Li
  • Publication number: 20080064249
    Abstract: An auxiliary device for a connector has a body, a wire unit and plug. The wire unit is mounted securely in the body and extends out of the body from a first end of the body. The plug is formed on a second end of the body and is perpendicular to the wire unit. Therefore, the position of the wire unit is fixed when the plug is inserted into a socket.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 13, 2008
    Applicant: CYBER POWER SYSTEM INC.
    Inventors: Lien-Hsun Ho, Yuan-Liang Hsu, Shou-Ting Yeh, Chuan-Hsing Wu, Tung-Yuan Chen, Chao-Yi Wu
  • Publication number: 20080060044
    Abstract: A personal video recorder (PVR) system includes a processing unit, a system memory coupled to the processing unit by a system memory bus, and an insertion module being coupled to the processing unit for inserting a packet into a PVR bit stream according to packet information. During a packet insertion operation, the processing unit is for reading data from the system memory, processing the data to generate the packet insertion information, and directly transferring the packet insertion information to the insertion module. By directly transferring the packet insertion information generated by the processing unit to the insertion module, memory bandwidth requirements of the system memory are reduced, and data access of the system memory is improved.
    Type: Application
    Filed: September 4, 2006
    Publication date: March 6, 2008
    Inventors: Chien-Chung Huang, Freimann Felix, Yuan-Liang Cheng, Tung-Hao Huang
  • Patent number: 7329946
    Abstract: A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: February 12, 2008
    Assignee: Intel Corporation
    Inventors: Jianqi He, Yuan-Liang Li, Michael Walk
  • Patent number: 7321167
    Abstract: In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: January 22, 2008
    Assignee: Intel Corporation
    Inventors: Dong Zhong, Yuan-Liang Li, Jianggi He, Jung Kang, Prashant Parmar, Hyunjun Kim, Joel Auernheimer
  • Patent number: 7317622
    Abstract: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: January 8, 2008
    Assignee: Intel Corporation
    Inventor: Yuan-Liang Li
  • Publication number: 20070295818
    Abstract: A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.
    Type: Application
    Filed: June 22, 2006
    Publication date: December 27, 2007
    Inventors: Yuan-Liang Li, Jayashree Kar, David G. Figueroa, Dong Zhong
  • Publication number: 20070287321
    Abstract: A shell for an electrical appliance includes a base, a cover, and a plug-receiving assembly. The plug-receiving assembly includes a recess attached to the cover for receiving a plug of the electrical appliance. The recess has a bottom and two opposing sides. The bottom supports the plug, and the opposing sides have protrusions for retaining the plug in the recess. The plug-receiving assembly further includes a slanted guide formed on the bottom of the recess for guiding the plug in the recess. A user may remove the plug from the recess by the pulling an electrical wire attached to the plug to move the plug along the slanted guide and out from the recess. Additionally, the plug-receiving assembly may include a mounting grove adjacent to the slanted guide for retaining the electrical wire.
    Type: Application
    Filed: June 12, 2006
    Publication date: December 13, 2007
    Applicant: CYBER POWER SYSTEM INC.
    Inventors: Hsiung-Kuei Cheng, Jian-Hung Chen, Yuan-Liang Hsu, Lien-Hsun Ho
  • Publication number: 20070258586
    Abstract: A method of processing a transport stream having a plurality of packets to output a protected transport stream includes providing a set of secret keys having a predetermined number of secret keys; generating a key indication value; selecting a secret key from the set of secret keys according to the key indication value to form a selected secret key; generating an encrypted packet based on the selected secret key and a packet in the transport stream by: encrypting the payload of the packet according to the selected secret key, and storing the key indication value in the sync field; and generating the protected transport stream based on the encrypted packet. Where each packet comprising a packet header and a payload, the packet header comprising a sync field, and the sync field carrying a preset sync pattern.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 8, 2007
    Inventors: Chien-Chung Huang, Freimann Felix, Yuan-Liang Cheng, Tung-Hao Huang
  • Patent number: 7286368
    Abstract: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: October 23, 2007
    Assignee: Intel Corporation
    Inventors: Dong Zhong, David G. Figueroa, Yuan-Liang Li, Michael M. Desmith
  • Publication number: 20070225826
    Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.
    Type: Application
    Filed: March 21, 2006
    Publication date: September 27, 2007
    Inventors: Chien-Chung Huang, Yuan-Liang Cheng, Tung-Hao Huang, You-Min Yeh, Chung-Yu Chang
  • Patent number: 7239299
    Abstract: A driving circuit of a liquid crystal display device includes a substrate, at least two driver integrated circuit (IC) chips located on the substrate, and an impedance device electrically connected between the two driver IC chips for reducing a difference between respective input voltages being input into the two driver IC chips.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: July 3, 2007
    Assignee: Chi Mei Optoelectronics Corporation
    Inventors: Yuan-Liang Wu, Hsin-Ta Lee, Wen-Chieh Lin
  • Publication number: 20070145829
    Abstract: A voltage regulating circuit has a first switch, a transformer and a second switch. The first switch has an input node, a first node and a second node. The transformer is connected to the switches has a first coil and a second coil. The first coil and the second coil respectively have an end, and the second coil is connected to the first coil in series at a node. The node between the first and second coils is connected to the second node of the first switch. The second switch is connected to the transformer and has a first node, a second node and an output node. The first node is connected to the end of the first coil. The second node is connected to the first node of the first switch. The transformer will not heat up when the transformer needs not to be used.
    Type: Application
    Filed: June 27, 2006
    Publication date: June 28, 2007
    Inventors: Shou-Ting Yeh, Lien-Hsun Ho, Yuan-Liang Hsu
  • Patent number: 7221046
    Abstract: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts, and an element having a plurality of resistive portions, each of the plurality of resistive portions being coupled to a respective one of the plurality of conductive contacts. The integrated circuit package may further include a decoupling capacitor having a plurality of capacitor pads, each of the plurality of capacitor pads being coupled to a respective one of the plurality of resistive portions.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Dong Zhong, David G. Figueroa, Yuan-Liang Li
  • Patent number: 7215530
    Abstract: In some embodiments, a capacitor includes a first conductive layer electrically coupled to a first terminal, a second conductive layer electrically coupled to a second terminal, a floated conductive layer disposed between the first and second conductive layers, and a plurality of non-conductive layers respectively disposed between each of the conductive layers. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 8, 2007
    Assignee: Intel Corporation
    Inventors: Yuan-Liang Li, David G. Figueroa, Nicholas L. Holmberg
  • Patent number: 7212395
    Abstract: According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: May 1, 2007
    Assignee: Intel Corporation
    Inventors: Yuan-Liang Li, David G. Figueroa, Farzaneh Yahyaei-moayyed, Dong Zhong